Extoll

GTS - GlobalFoundries´ Technology Summit 2024 is taking place this Wed Oct 16 in Shanghai. Meet us at EXTOLL´s exhibitor table – or reach out to sales@extoll.com to make an appointment. 👍 See you soon! 🤩 https://lnkd.in/eQUuZs_N #chiplets #semiconductor #extoll #gts24

🚀 Exciting News! 🚀 EXTOLL, a leading provider of high-speed and ultra-low-power SerDes and Chiplet connectivity, has been selected by Frontgrade Technologies, a leading provider of mission critical electronics for aerospace and defense, as a key SerDes IP block supplier for its ASIC development portfolio.   “This collaboration emphasizes EXTOLL´s strength in ultra-low power design, particularly in the 22nm process geometry. We are happy and honored to jointly work with Frontgrade, a renowned industry leader on aerospace and defense semiconductor solutions in harsh conditions,” says Dirk Wieberneit, CEO of EXTOLL.   EXTOLL´s IP is optimized to deliver highest speeds at smallest footprint and lowest power consumption, enabling a super energy-efficient solution for chiplet-based systems. The SerDes IP core supports line speeds up to 32 Gbps per lane and comes with generic support of various protocols and availability in 12 - 22nm process nodes.   “We are pleased to work with EXTOLL on their SerDes technology in 22nm,“ said Lorne Graves, Chief Technology Officer at Frontgrade Technologies. “Extoll’s innovations on this process node enable best-in-class power and performance that our customers need, which makes them a great fit for Frontgrade’s high-speed data transport framework.”   Please address your inquiries to sales@extoll.com and visit our website at www.extoll.com. #Semiconductors #Aerospace #Chiplets #SerDes #UltraLowPower #HighSpeed #ASICDevelopment #ArtificialIntelligence #AI #TechNews #Engineering #FutureTech #TechPartnerships

🚀 Exciting News! 🚀 EXTOLL, a leading provider of high-speed and ultra-low-power SerDes and Chiplet connectivity, has been selected by Frontgrade Technologies, a leading provider of mission critical electronics for aerospace and defense, as a key SerDes IP block supplier for its ASIC development portfolio.   “This collaboration emphasizes EXTOLL´s strength in ultra-low power design, particularly in the 22nm process geometry. We are happy and honored to jointly work with Frontgrade, a renowned industry leader on aerospace and defense semiconductor solutions in harsh conditions,” says Dirk Wieberneit, CEO of EXTOLL.   EXTOLL´s IP is optimized to deliver highest speeds at smallest footprint and lowest power consumption, enabling a super energy-efficient solution for chiplet-based systems. The SerDes IP core supports line speeds up to 32 Gbps per lane and comes with generic support of various protocols and availability in 12 - 22nm process nodes.   “We are pleased to work with EXTOLL on their SerDes technology in 22nm,“ said Lorne Graves, Chief Technology Officer at Frontgrade Technologies. “Extoll’s innovations on this process node enable best-in-class power and performance that our customers need, which makes them a great fit for Frontgrade’s high-speed data transport framework.”   Please address your inquiries to sales@extoll.com and visit our website at www.extoll.com. #Semiconductors #Aerospace #Chiplets #SerDes #UltraLowPower #HighSpeed #ASICDevelopment #ArtificialIntelligence #AI #TechNews #Engineering #FutureTech #TechPartnerships

🚀 Exciting News! 🚀 EXTOLL is thrilled to announce our partnership with BAE Systems for the STEAM PIPE project! 🌟 We are providing a power-optimized, very short-reach SerDes IP solution to advance microelectronics. This collaboration highlights our expertise in ultra-low power design, especially in the 12nm process geometry. We are honored to work with BAE Systems to deliver critical solutions for this demanding sector. Our SerDes IP core supports line speeds up to 32 Gbps per lane, ensuring the highest speeds with the smallest footprint and lowest power consumption. For more details, visit our website at www.extoll.com or contact us at sales@extoll.com. #Chiplets #Microelectronics #Technology #SerDes #EXTOLL #BAESystems

☝️Check out our latest news: #extoll collaborates with #psiquantum as a key partner for high-speed SerDes IP 👏 #quantencomputing #chiplets #serdes Read more: https://bit.ly/4cV63hS

👉Upcoming EPI Forum open for registration As a technology provider and proud member of the EPI consortium, EXTOLL would like to inform about the upcoming EPI Forum on 9 and 10 October 2024 in Barcelona, Spain. https://lnkd.in/d_ieNDh3 EPI Forum will gather experts from the HPC ecosystem, stakeholders in the field and EPI researchers and engineers to discuss and present EPI’s achievement so far and future developments in the Initiative. 👍Registration for the event is now open.

🌟 Join us at the GTS Technology Summits 2024! 🌟 We are thrilled to announce that EXTOLL will be a Gold Partner at GlobalFoundries’ Technology Summits 2024! 🚀 Catch us at our Exhibitor table at all three signature events, where industry leaders and innovators come together to share insights and shape the future of technology. Don’t miss out on this opportunity to connect and gain new perspectives! 📅 Event Dates: Aug 29, 2024: Santa Clara, USA Link Sep 18, 2024: Munich, Germany Link Oct 16, 2024: Shanghai, China We can’t wait to see you there! Reach out to us at sales@extoll.com to schedule a meeting. Let’s innovate together! 💡 #globalfoundries #gtstechnologysummit #gts

The @Universal Chiplet Interconnect Express (UCIe) announced the release of its UCIe 2.0 specification. UCIe 2.0 continues to advance an open chiplet ecosystem by supporting 3D packaging, manageability system architecture and more. The latest specification also offers higher bandwidth density and improved power efficiencies while remaining fully backward compatible with the UCIe 1.1 and UCIe 1.0 specifications. 👉 The link for the press release can be found here and also in the comments: https://bit.ly/43SiUN5

The @Universal Chiplet Interconnect Express (UCIe) announced the release of its UCIe 2.0 specification. UCIe 2.0 continues to advance an open chiplet ecosystem by supporting 3D packaging, manageability system architecture and more. The latest specification also offers higher bandwidth density and improved power efficiencies while remaining fully backward compatible with the UCIe 1.1 and UCIe 1.0 specifications. 👉 The link for the press release can be found here and also in the comments: https://bit.ly/43SiUN5

We're #hiring a new (SENIOR) MIXED-SIGNAL VERIFICATION ENGINEER (M/F/D) in Mannheim, Baden-Württemberg. Apply today or share this post with your network.