VLSIVersity

🚀 We're Hiring Experienced Design Verification Professionals! 🚀 Join Mirafra to contribute to impactful projects and collaborate with global teams. We are looking for skilled Design Verification Engineers for multiple locations with expertise in the following areas: 🔹 Design Verification Roles: GLS - 5+ Years PCIe - 5+ Years NOC - 5+ Years SOC - 5+ Years UFS - 5+ Years CPU - 6+ Years HSIO - 5+ Years CHI - 3+ Years DV Leads - 8+ Years AMS Verification - 2+ Years FPGA Emulation - 4+ Years 🔹 Onsite Opportunities: Design Verification with Specman (Germany/WFH) – 5+ Years Design Verification for USA (Valid work permit required) – 8+ Years If you have the skills and experience, we want to hear from you! 💬 Send your resume to pkalavathi@mirafra.com Radhika Srihari Ridhima Deopa Sonal Sanas Rajasree Ch #Hiring #DesignVerification #EngineeringJobs #VLSI #VerificationJobs #Semiconductor #Mirafra

#)Understanding Clock Domain Crossing (CDC) in Digital Design In digital design, especially in ASIC and FPGA development, Clock Domain Crossing (CDC) refers to the transfer of data between different clock domains, which is essential in systems with multiple clocks to manage high performance, low power, and complex functionality. Why CDC Matters: When signals cross from one clock domain to another, there’s a risk of metastability, which can cause unpredictable behavior, data corruption, or even system failures. This is why CDC verification is an integral part of the design flow. Credits: #)https://lnkd.in/guq66KGb #ASIC #FPGA #ClockDomainCrossing #DesignVerification #DigitalDesign #VLSI #Electronics #Engineering

Job Title: DV Engineer (Multiple Job Openings) Job Description: I am currently looking for an experienced DV Engineer with 6 - 12 years of expertise in Digital Design and SystemVerilog with UVM along with hands-on work experience on USB, CLink and DDR protocol. Key Responsibilities: Utilize strong Digital Design concepts to contribute to our projects and apply SystemVerilog fundamentals in daily tasks. Leverage extensive experience with DDR, USB Protocol on next-gen #snapdragon powered Mobiles and Laptops. Qualifications: B.E/M.E in Engineering with 6+ years of experience in DV. Strong knowledge of Digital Design concepts. Proficiency in SystemVerilog. Hands-on work experience with DDR and USB Protocol. Application Process:  Short-listed candidates will be contacted for telephonic or face-to-face interviews. Note: Not considering applications from intern, fresher, or lesser work experience for this opening. #USB #DDR #hiring #uvm #Qualcomm

Want to pursue a career in design verification but worried about expensive courses? We've got you covered! 🚀 I’m excited to share that we are providing a comprehensive Design Verification (DV) course for free, covering essential topics: 🔹 Digital Electronics: https://lnkd.in/gzz6kvTd 🔹 Static Timing Analysis (STA): https://lnkd.in/g5BAsqrA 🔹 Verilog:  https://lnkd.in/gc2_muaa 🔹 SystemVerilog: https://lnkd.in/g-fcdBzr 🔹 UVM (Universal Verification Methodology): https://lnkd.in/gqMFY563 Do subscribe to our channel : https://lnkd.in/gMzbNCBa Access these in-depth courses and build your expertise at no cost. Let's elevate your VLSI skills and open doors to new opportunities! #DesignVerification #VLSI #FreeCourses #Learning

Mirafra is hiring Various VLSI opportunities at Hyd/Bang Please share the resume to swarnamanjari@mirafra.com #opentowork #designverification #rtl #fpga #nvme #pcie #GLS #C++#Systemverilog #UVM #FUSA #NOC

Hi all, Exciting opportunities at Synopsys! Join our dynamic team and be part of cutting-edge projects in the tech industry. We have openings for, - Emulation Engineers : 4+ ( Bangalore, Hyderabad, Noida) - DFT Engineers: 5+ (Bangalore) - RTL Engineers: 3+ (Bangalore, Hyderabad, Noida) - DV Engineers: 3+ (Pune, Bangalore, Hyderabad, Noida) - PD Engineers : 3+ (Bangalore, Hyderabad) - STA Engineers : 5+ years (Bangalore, Hyderabad) - Layout design Engineer : 3+ years (Bangalore, Hyderabad, Noida, Pune) - Analog design : 3+ years ( Bangalore, Hyderabad, Noida) Please mail me your resume at bibinsaju95@gmail.com for referrals. Mail me for queries. I won’t be able to reply on LinkedIn. Note : Please do mention the domain, relevant years of experience and location in the subject. #VLSI #PD #DV #DFT #RTL #STA #referral

Join our team @ Microsoft We're looking for passionate individuals who are ready to make a difference!! #DV #Hiring

We are #hiring. SOC Verification Engineers with 4+ Years of Experience Know anyone who might be interested? What's make you stand out : * Should have a good understanding of verification flow, challenges, and requirements of functional verification * Have working experience on AMBA interface protocols (AXI, AHB, APB) * Hands-on experience on working one or more of the following protocols is a must – UART, I2C, SPI, QSPI, I3C, eMMC, CAN, * Hands-on experience working with one or more of the following protocols is desired – PCIe, USB, DDR, LPDDR, GBE, SATA Ridam Jaiswal Ashish Deshpande #ASIC #IP #SOC #Verification #Bangalore #Pune #AMBA

We’re looking for passionate #DesignVerification Engineers, Seniors, Leads, and Managers! Locations: Bangalore, Hyderabad, Ahmedabad, Noida, USA (with a valid visa) Experience: 4-20 years 📧 Interested candidates, please send your resume to pkalavathi@mirafra.com #Hiring #JobOpening #CareerOpportunity #DesignVerificationJobs #TechJobs #JoinUs Radhika Srihari Ridhima Deopa Sonal Sanas Rajasree Ch