Antmicro

Along embedded world Exhibition&Conference North America, The Zephyr Project is hosting a meetup this Wednesday at  NXP Semiconductors in Austin. Join us to learn a new exciting tool that can help you visualize and build complex, multi-node systems with #ZephyrRTOS. Register here: https://lnkd.in/dGFi8yrJ

Real-time applications, such as space and automotive, require configurable standardized interrupt controllers. Renode launched the new Core-Local Interrupt Controller (CLIC) for the RISC-V ISA, which is designed to provide for low-latency and pre-emptive interrupts for RISC‑V systems. Discover more here: https://hubs.la/Q02TRX_50

Easily integrate #Renode into your GitHub #CI pipelines and automate advanced test suites on hundreds of available simulated hardware blocks with the Renode GitHub Action. Get logs, reports and execution metrics. See how we use it and try it out: https://lnkd.in/dfKJ-Yfb #Caliptra CHIPS Alliance The Zephyr Project

Watch our Vienna #OSSummit lightning talk on #opensource fleet management in #ZephyrRTOS with Antmicro's #RDFM framework featuring seamless #OTA updates with delta packages: https://lnkd.in/dnM-pQBQ The Zephyr Project Kate Stewart Maemalynn Nokdhes Meanor Tracey Cramer Li The Linux Foundation Linux Foundation Europe

Meet us at #RISCVSummit North America this week to learn about RISC-V International and CHIPS Alliance collaboration and the synergies offered by the open ISA and open silicon/hardware design in projects like #Caliptra RoT AMD Google Microsoft NVIDIA The Linux Foundation Calista Redmond Lori Servin Rob Mains Benjamin S. https://lnkd.in/eHiEetVa

Leveraging the extensive tracing capabilities offered by our #Renode simulation framework, we created a generic cache usage analyzer that can be used in architectural exploration and early prototyping with Renode: https://lnkd.in/gyCZSjNT RISC-V International Calista Redmond TRISTAN

Our #Renode co-simulation framework now includes support for the new CLIC standard in #RISCV, providing features that enable low-latency interrupt handling as an alternative to existing interrupt controllers. Find out how to use fast interrupts in real-time applications: https://lnkd.in/dDiG7qir RISC-V International Calista Redmond TRISTAN

A large and growing library of 3D rendered hardware components makes it easy to visually explore the make-up of your planned or existing devices. Devices in Antmicro's System Designer feature hot areas that are highlighted and clickable on hover, with instant access to block diagram, component list, documentation, related devices with the same processing elements, (e.g. SoC), supported software and a range of readily available demos via the #Renode HW/SW co-simulation framework. Check out this example of our #RISCV-based Microchip Technology Inc. #PolarFire System-on-Module: https://lnkd.in/dM7TgwF6 And read more about interactive component highlighting on our blog: https://lnkd.in/dmwDa659 RISC-V International Calista Redmond Lori Servin Brian Colgan Martyn Stroeve John Chasko Cyril Jean Judd Bard Minh Uyen Nguyen Rich Ford Stephanie Wang Ted Speers Tim Morin diptesh nandi Rodger Richey Krishnakumar (KK) Ramamoorthi

Introducing sv-bugpoint, an #opensource tool for identifying minimal bug-inducing #SystemVerilog code fragments that can be then shared externally to improve debugging in #Verilator, The OpenROAD Project & any other SV tool: https://lnkd.in/dkPE9try CHIPS Alliance RISC-V International Google #UVM TRISTAN

Watch our #ZephyrTechTalk with Benjamin Cabé on how our #opensource tools and methodologies help streamline development of complex #ZephyrRTOS-based projects with System Designer: from generating HBOMs, 3D renders to testing in #Renode simulation https://lnkd.in/dK6XjyT6 The Zephyr Project The Linux Foundation Kate Stewart Maemalynn Nokdhes Meanor Susan Remmert