DBSI Services

Hi Connections, Hope you are doing well!!! I am working to fill up the position of Hardware Engineer in Houston, TX. If interested please share your updated resume at rahul.bhagat@dbsiservices.com or you can reach me at 908-615-1717 at your earliest convenience. Please feel free to DM me if you have any queries or recommendations. #like #comment #share #resume #help #network #reference #hardwareengineer #pcb #pcbdesign #hiring #usahiring

Hi Connections, Hope you are doing well!!! I am working to fill up the position of Manufacturing Engineer in Weirton, West Virginia. If interested, kindly apply through the below link or you can share your updated resume at amit.tiwari@dbsiservices.com. Also, you can reach out to me at 908-615-1717 at your earliest convenience. Please feel free to DM me if you have any queries or recommendations. #like #comment #share #resume #help #network #reference #manufacturing #manufacturingengineer #battery #energystorage #leanmanufacturing #sixsigma #newjob #jobhiring #usajobs #usahiring #hiring

Hi Connections, Hope you are doing well!!! I am working to fill up a full-time direct hire position as a Front-End ASIC Design Engineer in Bangalore, India. If interested, kindly share your updated resume at amit.tiwari@dbsiservices.com. Please feel free to DM me if you have any queries or recommendations. Job Title: Design Verification Engineer Location: Bangalore, India   Job Description   Primary Responsibilities Include: Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practices. Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action. Responsible for verification of ASIC designs To include such things as: o  Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team. o  Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible for Debugging Designs for High throughput, Low Latency of Pipeline, and Dynamic Power Management at the full system level. o  Setup Verification Regression suites at the RTL Level & Corresponding Netlist Level after Synthesis to test any/all Corner case conditions. Necessary Qualifications: BS or MS in Computer Science or Electrical Engineering. 5-10+ years of industry experience bringing silicon ICs into high-volume production. Must have strong experience with UVM. Must have a full chip verification experience Experience of leading a single project. Knowledge of industry-standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Real Time. Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification) Expertise in writing Perl / Python, awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers. Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion, and test pattern generation Experience with low-level programming of systems in C/C++. Experienced in writing scripts in languages such as Perl, Python, and Tcl. Functional understanding of constrained random verification process, functional coverage, and code coverage. Low power verification UPF  

Hi Connections, Hope you are doing well!!! I am working to fill up a full-time direct hire position as a Front-End ASIC Design Engineer in Bangalore, India. If interested, kindly share your updated resume at amit.tiwari@dbsiservices.com. Please feel free to DM me if you have any queries or recommendations. Job Title: Front-End ASIC Design Engineer Location: Bangalore, India Job Description Responsibilities Include but are not limited to: ·        Support customer’s design through all phases of ASIC execution at Socionext. ·        Ensure designs meet product Performance-Power-Area-Schedule requirements. Tasks may include Architecture/micro-architecture; Logic Design; RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing-closure; Contributing to and supporting Verification; Supporting Firmware and FPGA teams; Silicon bring-up. ·        Ensure deadlines for project milestones are met while maintaining quality. ·        Work effectively with internal and external (including customer and vendors) teams  (Note: Socionext has teams located globally). ·        Display a results-focused attitude and accomplish Company/team goals.   Required/Desired Qualifications: ·        Bachelor’s Degree in EE or similar degree. ·        5+ years of professional design experience, provided the work experience is solid micro-architecture and front-end design. ·        Hands-on ASIC front-end design, ideally in design services environments (product backgrounds acceptable). ·        Skills Required – Micro-architecture at module/sub-system/chip-level; digital design of complex modules/sub-systems, with solid understanding of clock-domain crossings; integration of IPs/modules/sub-systems designed by internal/external teams; experience using AMBA bus protocols; System Verilog experience; Lint and CDC execution and analysis; writing timing constraints and timing analysis; excellent debug skills; customer support. ·        Technical document writing skill ·        Teamwork, dedication, collaborative, strong communications, and interpersonal skills. ·        Ability to meet stringent deadlines and project timelines. Skills Strongly Desired – SoC Architecture experience. Experience and domain knowledge in at least 2-3 of these: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low-power design and verification; high-speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe; Machine-learning / AI; FPGA. #like #comment #share #resume #help #network #reference #soc #asic #frontend #cpu #rtlintegration