Noblesoft Technologies

System-on-Chip Design Engineer

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Astrid Morgan

Astrid Morgan

Hiring

Role: SOC RTL Design Engineer

Location: Remote

Position: Contract


Role Description:

Contribute to micro-architecture specification for SoC design block

Participated in 2-3 SoC projects

Participate in SoC Chip Architecture specification reviews

Must have extensive experience in Micro-architecture design for SoC sub-blocks

Interact with SoC integration, verification, and physical design teams and also with IP vendors

Extensive experience in SoC RTL coding (Verilog or System-Verilog).

Experience in RTL Code Linting and CDC checks.

Experience in RTL integration using Industry standard tools, is an added advantage

Handle complete responsibility of an entire block starting from Micro-architecture specifications, RTL implementation, Linting, CDC, Synthesis/STA

Experience in low power design techniques

Good understanding of DFx design techniques

Good appreciation of AXI/AHB bus protocol, GigBE, USB, NAND Flash Technology, PCIe Gen2/3 Host interface, DDR2/3 memory interfaces etc.

Experience in PCIe, HBM memory protocol is Preferred

  • Seniority level

    Mid-Senior level
  • Employment type

    Contract
  • Job function

    Information Technology
  • Industries

    Manufacturing

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