Technical Specialist

Role: Technical Specialist

Location:Remote

Duration: Long Term Contract

Statement Of Work

Be part of a dynamic and skilled IBM research team developing and implementing an accelerator solution for deep learning workloads based on the use of advanced agile RTL/FPGA generation (and optimization). The design will consist of the RISC-V cores, DNN accelerator, memory block, IO blocks and Fully Homomorphic Encryption (FHE) engine. The scope will cover individual tile logic design, place and route and functional verification to ensure a working chip for a defined set of workloads. These design blocks will be integrated via ESP design methodology. ESP is an open-source research platform for heterogeneous system-on-chip design that combines a scalable tile-based architecture and a flexible system-level design methodology developed at Columbia University. ESP provides three accelerator flows: RTL, high-level synthesis (HLS), machine learning frameworks. All three design flows converge to the ESP automated SoC integration flow that generates the necessary hardware and software interfaces to rapidly enable full-system prototyping on FPGA. The candidate will extend the ESP capabilities to integrate newly developed tile blocks (such as FHE blocks) and implemented the accelerator SoC design using the enhanced ESP methodology.

Task Description

• Job Duty 1 – Architecture level and logic designs for specified functional specifications and requirements, using industry standard (EDA) tools. Designs include RISC-V microprocessor cores, DNN accelerators, memory blocks, IO blocks such as UCIe and Fully Homomorphic Encryption (FHE) engine. Tasks include RTL designs, functional verification including FPGA-based emulations.
• Job Duty 2 – Use commercial EDA tools to implement these tile blocks using RTLs created Job Duty 1 to generate GDS outputs. Work closely with other layout engineers to verify the layouts for the various design blocks.
• Job Duty 3 - Digital circuit design using hardware description language and cadence digital implementation tools for PPA (Performance, Power and Area) optimization.
• Job Duty 4 - Debug and solve problems in a team environment.
  
  

Required Skills/Level Of Experience

• Strong experience in architecture level design space exploration for performance and power optimization.
• Proficiency in at least one hardware description language: Verilog, SystemVerilog, VHDL and cadence digital implementation tools: Genus/Innovous
• Simulation skills for full chip verification required (creating test bench, design partitioning, etc.)
• FPGA implementation and emulation methodology
• Ability to debug errors and solve problems in a team environment, independently, but not in isolation.
• Familiarity with ESP design methodology, open-source research platform for heterogeneous system-on-chip design that combines a scalable tile-based architecture and a flexible system-level design methodology
• Fluent English (both verbal and written) and strong communication and presentation skills.
  
  

Nice To Have Skills

• Preferred: Experience with architecture level design space exploration.
• Preferred: RTL coding and FPGA implementation using commercial tools
• Preferred: FPGA-based emulation experience using commercial tools
• Preferred: Experience with advanced sub-micron semiconductor technology nodes (sub 10nm)