AGNIT Semiconductors Pvt Ltd’s Post

#we #Hiring #Physical #Design #PD #Experience: 3 to 8 years #Bangalore #Hyderabad #Singapore #Malaysia #Job #Description: 1. Physical design from the netlist to GDSII, including floor planning, place route, clock tree synthesis, timing ECO, and design closure. 2. candidate should have hands-on experience in ICC or Innovus with Client projects. 3. Physical Design Planning : Closely Collaborate with chip architects and logic designers to understand the   design goals, constraints, and specifications. Develop a physical design plan that outlines the steps and resources needed for successful implementation.                          4. Floor planning: Create a floor plan that defines the placement of different functional blocks and components on the semiconductor die to optimize power, performance, and area (PPA). 5. Placement: Place and optimize logic cells, memory elements, and other IP blocks on the chip according to the floorplan. Balance trade-offs between area, timing, and power consumption. 6. Clock Tree Synthesis (CTS): Design and implement clock distribution networks to ensure synchronized clock signals throughout the chip, minimizing clock skew and jitter. VLSI Professionals Group Jamadagni Physical Design PRAXIEN TECHNOLOGIES Praxien Tech #vlsi #pd #Design #Engineer #ECO #ICC #Innovus #Floor #Planning #Power #Performance #CTS #Placement #Jitter #Skew #GDSII #netlist

Good opportunity

Transforming my skills in circuit design! Participated in the 'Circuit Voyage' workshop at Sri Krishna College of Technology, Coimbatore during AVANTAA'24. -Gained practical knowledge and experience in circuit design and development. - Explored the applications of circuit design in various industries. - Learned about the latest software and tools used in circuit design. - Enhanced my skills and knowledge in circuit design and development. #CircuitVoyage #AVANTAA24 #CircuitDesign"

great opportunities

Analog Mixed Design Engineer / Lead - 6+ Position.    Skills:    AMS Design , 1.  High speed interface design PLL/DLL, Phase Interpolator, CDR). Speeds -16Gbps High speed interface design block level understanding(Ex blocks include Duty cycle corrector, Sampler, Serializer/Deserializer, PLL/DLL, Phase Interpolator, CDR). Speeds -16Gbps and above. Design of custom-digital blocks to meet slew/delay requirements and flops for setup/hold margins etc. Effect of layout on high speed data/clock paths. Ability to judge poor layouts and suggest improvements. Advanced level expertise on cadence tools like Maestro, Virtuoso, spectre netlist hacking. VerilogA modeling for measurements purpose and modeling few blocks for quicker simulation time. Ability to organize data in a understandable way and present to customer for review. please do the share the basic information in the below format each submission without fail. Ekata M. #analogdesign #analog #ams #mixedsignal #hyderabadjobs #hyderabad #hyderabadhiring #hyderabadjobseekers #hyderabad #bangalorejobs #bangalore #bangalorehiring #bangalorejobseekers #bangalore #itjobs #itjobsearch #itjobopportunity #itjobopening

Hi Buddy😎 we are looking for physical design engineer with strong RTL2GDS skills.(location for #bangalore /#hyderabad /#noida ) Roles & Responsibilities defined below: 1. #sta / Synthesis (Static Timing Analysis): Perform static timing analysis to ensure the design meets the specified timing constraints. Work closely with the design team to identify and resolve timing issues. Optimize the design for performance and power efficiency. SDC constraints development & clean -up . 2. #pnr (#placement and #router ): Execute place and route activities to achieve optimal physical implementation of the ASIC. Collaborate with the physical design team to address floor planning, placement, and routing challenges. Drive physical optimization techniques for area, power, and performance. Should have descriptive knowledge on signoff & ECO generation. 3. #asic Design: Contribute to the overall ASIC design flow from RTL to GDSII. Work on complex design challenges and propose innovative solutions. Collaborate with cross-functional teams, including RTL designers and verification engineers. 4.#methodology and #tool Development: Stay abreast of the latest advancements in physical design methodologies and tools. Contribute to the development and improvement of physical design methodologies. #pnr #pv #innovación #job #emir #synthesis #tessolve

Excited to share that I have completed a 6-day workshop on " OpenROAD for Low-Cost ASIC Design & Rapid Innovation " organized by NINELabs @IIT Guwahati During the Workshop, I learned the complete flow of RTL to GDSII conversion process and also learned to use industry-standard tools like Yosys, Klayout, etc. I am very grateful to Amol Boke sir, and Vijayan Krishnan sir for their invaluable guidance and mentorship throughout the session. Also thankful to Prof. JOHN JOSE sir, Prof. Chandan Karfa sir, Prof. V. Kamakoti sir, and Prof. Madhav Desai sir for their amazing talks. Special thanks to Prof. Gaurav Trivedi sir, and Prof. Aryabartta Sahu sir for conducting such worthy workshop Here's a brief overview of my learning journey: 1)RTL Design: Delved into Register-Transfer Level (RTL) design principles, laying the foundation for subsequent stages in the ASIC design flow. 2)Synthesis with Yosys: Learned to leverage Yosys for synthesis, transforming the RTL description into a logical netlist. 3)Floorplanning and Placement: Explored the crucial aspects of floorplanning and placement to optimize physical design. 4)Routing with OpenROAD: Navigated the intricacies of routing using OpenROAD, ensuring a robust and efficient design. 5)Physical Verification with KLayout: Utilized KLayout for physical verification, ensuring the design adheres to layout constraints. 6)Final GDS Generation: Completed the RTL to GDS conversion, culminating in the generation of the final Graphic Design System (GDS) file. This immersive workshop not only enhanced my technical skills but also provided insights into the collaborative and innovative culture fostered by Nine Labs. Looking forward to applying these learnings in future projects and contributing to the realm of low-cost ASIC design. . . . . . . . . The OpenROAD Project #opensource #vlsi #vlsijobs #vlsidesign #rtldesign #gds2flow #asicdesign #lowcost #asic #verilog #linuxcommands #electronicdevices #electronicengineer #electronics #electronicsmanufacturing

Hiring Design Verification Engineer Years of experience: 6 to 15 years Area of expertise: System Verilog and UVM, PCIe, Ethernet Positions: Senior Project Engineer's to Tech Lead Locations: Bangalore, Hyderabad and Ahmedabad #bengaluru #bengalurujobs #hyderabad #hyderabadjobs #ahmedabad · BE/ B.Tech/ Master degree in Electrical Engineering or Computer Science · 6+ years of experience in pre-silicon RTL Verification /IP Verification / SOC verification · Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas 1. System-on-a-chip verification with multiple CPUs and fixed function units with AXI or NOC interconnects 2. Verification of embedded CPUs such as ARM, Tensilica, MIPS CPUs and interconnect subsystem through C/Assembly language tests 3. Verification of industry standard serial interfaces such as MIPI, USB, PCIe using industry standard VIP components. 4. Ethernet Packet Processors, buffer managers, DMA engines etc.... 5. PHY layer verification of serial interfaces such as Ethernet, PCIe, USB etc. 6. Solid Linux environment skills including the use of Perl, Python or TCL to write/debug CAD tool scripts. #rtlverification #socverification #ipverification #presiliconverification #uvm #systemverilog #pcie #ethernet #arm #rtl #buffer #dma #mips #presilicon #chipverification #designverification

Excited to share that I have completed a 6-day workshop on " OpenROAD for Low-Cost ASIC Design & Rapid Innovation " organized by NINELabs @IIT Guwahati During the Workshop, I learned the complete flow of RTL to GDSII conversion process and also learned to use industry-standard tools like Yosys, Klayout, etc. I am very grateful to Amol Boke sir, and Vijayan Krishnan sir for their invaluable guidance and mentorship throughout the session. Also thankful to Prof. JOHN JOSE sir, Prof. Chandan Karfa sir, Prof. V. Kamakoti sir, and Prof. Madhav Desai sir for their amazing talks. Special thanks to Prof. Gaurav Trivedi sir, and Prof. Aryabartta Sahu sir for conducting such worthy workshop Here's a brief overview of my learning journey: 1)RTL Design: Delved into Register-Transfer Level (RTL) design principles, laying the foundation for subsequent stages in the ASIC design flow. 2)Synthesis with Yosys: Learned to leverage Yosys for synthesis, transforming the RTL description into a logical netlist. 3)Floorplanning and Placement: Explored the crucial aspects of floorplanning and placement to optimize physical design. 4)Routing with OpenROAD: Navigated the intricacies of routing using OpenROAD, ensuring a robust and efficient design. 5)Physical Verification with KLayout: Utilized KLayout for physical verification, ensuring the design adheres to layout constraints. 6)Final GDS Generation: Completed the RTL to GDS conversion, culminating in the generation of the final Graphic Design System (GDS) file. This immersive workshop not only enhanced my technical skills but also provided insights into the collaborative and innovative culture fostered by Nine Labs. Looking forward to applying these learnings in future projects and contributing to the realm of low-cost ASIC design. The OpenROAD Project #opensource #vlsi #vlsijobs #vlsidesign #rtldesign #gds2flow #asicdesign #lowcost #asic #verilog #linuxcommands #electronicdevices #electronicengineer #electronics #electronicsmanufacturing