Amr Hassan’s Post

Excited to announce the completion of my Digital Verification Diploma using SystemVerilog and UVM , under the guidance of Eng. Kareem Waseem! This course provided me with important knowledge and hands-on experience in Digital Verification. The main topics explored: - Verification trends, planning, and design requirement extraction - SystemVerilog data types, subroutines, and interfaces - SystemVerilog assertions and threading - Fundamentals of object-oriented programming - Code coverage - Constrained random stimulus generation - Functional coverage - UVM structure, components, and configuration - UVM communication, sequences, phasing, TLM, and factory - Introduction to formal verification using property checking and equivalence checking - Hardware-assisted verification platforms, including FPGA-based prototyping and emulation As part of the diploma, I completed two challenging final projects: 1. Developing a class-based SystemVerilog testbench for asynchronous FIFO. (https://lnkd.in/d-W5hra3) 2. Creating a complete top-level UVM environment for a synchronous FIFO. (https://lnkd.in/d9ujQUNb) This experience has significantly enhanced my skills in digital design verification, and I’m eager to apply this knowledge in future opportunities. A special thanks to Eng. Kareem Waseem for the invaluable guidance and his support throughout this journey! #digitalverification #systemverilog #uvm #formalverification #objectorientedprogramming #hardwareverification #constrainedrandom #functionalcoverage #assertions

I am thrilled to announce that I have successfully completed the Digital Verification Diploma provided by Eng. Kareem Waseem (digital verification team lead at Si-Vision) This learning journey was challenging and rewarding, providing me with an exceptional wealth of experience and knowledge in the Digital Verification Field. The Diploma covered important topics in this challenging field such as: ●    Verification Trends, Planning & design requirements extraction ●    SystemVerilog Data Types, Subroutines & Interfaces ●    SystemVerilog Assertions & Threads ●    Basics of Object-Oriented Programming ●    Code Coverage ●    Generation of Constrained random Stimulus ●    Functional Coverage ●    UVM Structure Overview & Components ●    UVM Component Configuration, Communication & Sequences ●    UVM Phasing, TLM & Factory ●    Basic understanding of formal verification techniques, FPGA-based prototyping and emulators In addition, doing several practical labs and assignments on each topic has ensured the utmost understanding and dealing with them. And finally, Wrapping Up the whole Diploma with two challenging Final Projects which are 1) Developing a class-based SystemVerilog testbench for a FIFO . 2) Developed a complete top-level UVM environment for Synchronous FIFO . https://lnkd.in/dTeVErPB I would like to express my heartfelt gratitude to Eng. Kareem Waseem and his helpfull assistants Eng. Magdy Ahmed , Eng. Mustafa Ibrahim , Eng .Mahmoud Adel for their exceptional efforts, dedication, and insightful guidance in helping us to get the most out of this Diploma. #digitalverification #systemverilog #uvm #icdesign

I'm excited to announce that I have successfully completed the Digital Verification Diploma under the guidance of Eng. Kareem Waseem, Digital Verification Team Lead at Si-Vision. This program has been an immensely rewarding journey, providing me with a deep and comprehensive understanding of the digital verification field. The diploma covered critical topics, including: ▪️ Verification Trends, Planning & Requirements Extraction ▪️ SystemVerilog: Data Types, Subroutines, and Interfaces ▪️ SystemVerilog Assertions (SVA) and Multithreading ▪️ Object-Oriented Programming (OOP) Fundamentals ▪️ Code and Functional Coverage ▪️ Generation of Constrained Random Stimulus ▪️ UVM: Structure Overview, Components, Sequences, Phasing, TLM, and Factory Patterns ▪️ Basics of Formal Verification, FPGA-based Prototyping, and Emulation The program also included practical labs and assignments, ensuring hands-on experience in every aspect of verification. To conclude this enriching learning experience, I successfully completed two final projects: 1) Developed a class-based SystemVerilog testbench for a FIFO design. 2) Created a top-level UVM environment for verifying a Synchronous FIFO. I want to extend my sincere gratitude to Eng. Kareem Waseem and the support of Eng. Magdy Ahmed and Eng. Mustafa Ibrahim for their invaluable mentorship, dedication, and guidance throughout this program. #DigitalVerification #SystemVerilog #SVA #UVM #ICDesign #FPGA #FormalVerification

I'm excited to share that I’ve completed a Digital Verification Diploma focused on SystemVerilog and UVM, under the guidance of Eng. Kareem Waseem! During this program, I deepened my knowledge in several key areas, including: ●   SystemVerilog data types, threading, interfaces, and subroutines ●   Building functional coverage models and analyzing RTL code coverage ●   Writing SystemVerilog assertions and understanding object-oriented programming fundamentals ●   Generating constrained random stimulus for verification ●   Applying simulation-based verification techniques with UVM ●   Navigating UVM structures, components, sequences, configurations, and phasing ●   Grasping TLM and factory methods in UVM ●   Gaining an introduction to formal verification techniques This experience has greatly sharpened my skills in digital design verification, and I’m excited to apply what I’ve learned to new opportunities ahead. Huge thanks to Kareem Waseem for his excellent mentorship and to Mohamed Khaled_ for all the support throughout this journey! #DigitalVerification #SystemVerilog #UVM #ContinuousLearning #CareerDevelopment

Finally, I’m thrilled to announce that I have received my certificate for completing My Digital Verification Diploma using SystemVerilog (SV) and Universal Verification Methodology (UVM)! 🎉 This six-week journey was not only challenging but incredibly rewarding. Working on the verification of Syncronos FIFO using both SV and UVM deepened my understanding of complex verification processes and significantly enhanced my technical skills. This diploma has equipped me with essential knowledge, including: - Mastery of SystemVerilog datatypes and threading - Understanding of SystemVerilog interfaces and subroutines - Development of verification plans and design requirements extraction - Analysis of RTL code coverage results - Implementation of functional coverage models - Creation of SystemVerilog assertions - Basics of object-oriented programming - Generation of constrained random stimulus - Simulation-based verification techniques using UVM - In-depth knowledge of UVM structures, components, sequences, and configuration - Familiarity with UVM phasing, TLM, and factory patterns - Basic understanding of formal verification techniques, FPGA-based prototyping, and emulators I want to extend my heartfelt gratitude to Eng. Kareem Waseem for his mentorship throughout this process. His guidance was instrumental in my success and provided invaluable insights into the verification landscape. Receiving this certificate motivates me to continue my journey in digital verification, and I look forward to applying these skills to drive innovation in our industry! Thank you to everyone who has supported me along the way. Here’s to new opportunities and continuous learning! #ProudMoment #DigitalVerification #SystemVerilog #UVM #ContinuousLearning #CareerDevelopment

(وَعَلَّمَكَ مَا لَمۡ تَكُن تَعۡلَمُۚ وَكَانَ فَضۡلُ ٱللَّهِ عَلَیۡكَ عَظِیمࣰا﴾ I’m pleased to announce that I have successfully completed an intensive diploma program under the guidance of Eng. Kareem Waseem ,for which I am truly thankful. This program has significantly sharpened my skills in 𝗱𝗶𝗴𝗶𝘁𝗮𝗹 𝘃𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻, and I’m excited to share some of my key insights: 𝐌𝐚𝐣𝐨𝐫 𝐈𝐧𝐬𝐢𝐠𝐡𝐭𝐬 📌: • Expertise in SystemVerilog, including data types, threading, interfaces, and subroutines • Proficient in verification planning and requirements extraction • Conducted RTL code coverage analysis • Developed functional coverage models • Created SystemVerilog assertions • Generated constrained random test stimuli • In-depth understanding of UVM: structures, components, sequences, and configuration • Familiar with UVM phasing, TLM, and factory concepts • Basic knowledge of formal verification, FPGA prototyping, and emulation I would like to extend my sincere appreciation to Eng. Kareem Waseem for his invaluable support, as well as to Magdy Ahmed for his insightful contribution. #digitalverification #systemverilog #UVM #verification #FPGA #RTLdesign #functionalcoverage #assertions #SystemVerilogAssertions #randomtesting #constrainedrandom #verificationengineer

Hello peeps...🙏🏻..As a verification enthusiast i always wonder...🤔, "Why System Verilog and UVM are crucial in this field, though OVM can also be used" 🧐 , After searching, hete is the answer which i found appropriate..✅ .......................... SystemVerilog and UVM (Universal Verification Methodology) are essential in the verification field due to their advanced capabilities that streamline the development of complex digital systems. 1. SystemVerilog: A robust language that blends hardware description with verification features. Its powerful constructs (e.g., classes, randomization, assertions) make it ideal for creating highly flexible and reusable testbenches. 2. UVM (Universal Verification Methodology): A framework built on SystemVerilog that provides a standardized way to build scalable and reusable test environments. UVM promotes modularity and reuse, saving both time and effort in the verification process. ................... Together, they enable the efficient testing of today's increasingly complex SoCs and IP blocks, making them indispensable for design verification engineers! #SystemVerilog #UVM #Semiconductor #ChipDesign #Testbench #EDA #VLSI

الحمدلله حمداً كثيراً طيباً مباركاً فيه. Excited to share that I've successfully completed a 6-week intensive Digital verification diploma with Kareem Waseem! This journey has equipped me with: • Proficient in SystemVerilog datatypes, threading, interfaces, subroutines, and Object-Oriented Programming (OOP) principles. • Experienced in developing verification plans, extracting design requirements, functional coverage models, SystemVerilog assertions, and constrained random stimulus generation. • Knowledgeable in UVM structures, components, sequences, configuration, phasing, TLM, and factory, with simulation-based verification techniques, and basic understanding of formal verification, FPGA prototyping, and emulators. • Worked on many projects such as verification on ALSU design and FIFO design using both SystemVerilog and UVM. A big thank you to Eng. Kareem Waseem and to Eng. Mahmoud Adel for this comprehensive training, and I'm thrilled to apply these skills to future projects! #DigitalDesign #Verilog #HardwareDesign #EngineeringJourney #DigitalVerification #SystemVerilog

Excited to announce that I’ve officially completed my Digital Verification Diploma under the mentorship of Eng.Kareem Waseem! 🚀 During this journey, I’ve gained a wealth of knowledge and honed essential skills, including: ✅ Mastery of SystemVerilog Datatypes and threading. ✅ Understanding of SystemVerilog Interfaces and subroutines. ✅ Verification Plan Development and extracting design requirements. ✅ Analysis of RTL code coverage results. ✅ Implementing functional coverage models. ✅ Developing SystemVerilog Assertions. ✅ Basics of Object-Oriented Programming. ✅ Constrained random stimulus generation. ✅ Simulation-based verification techniques using UVM. ✅ Deep dive into UVM structures, components, sequences, and configuration. ✅ Understanding of UVM Phasing, TLM, and the factory. ✅ Basic knowledge of formal verification techniques, FPGA-based prototyping, and emulation. I also had the opportunity to apply these skills in projects like: • SV-Project---Synchronous-FIFO. Github Link: https://lnkd.in/gv2cz3fN • UVM-Project---Synchronous-FIFO. Github Link: https://lnkd.in/ggZyijyJ I'm excited to apply these skills in my next challenge and contribute to innovative digital verification projects! #DigitalVerification #SystemVerilog #UVM #RTL #FunctionalCoverage #VerificationEngineer #FPGA #FormalVerification #Simulation

(وَعَلَّمَكَ مَا لَمۡ تَكُن تَعۡلَمُۚ وَكَانَ فَضۡلُ ٱللَّهِ عَلَیۡكَ عَظِیمࣰا﴾ I'm thrilled to announce that I've successfully completed a comprehensive diploma under the supervision of Eng. Kareem Waseem, for which I am incredibly thankful. This program has significantly enhanced my skills in digital verification, and I couldn't be more excited to share my key takeaways: Key Highlights 📌 : · Mastery of SystemVerilog, including data types, threading, interfaces, and subroutines · Verification planning and design requirements extraction · RTL code coverage analysis · Implementation of functional coverage models · Development of SystemVerilog assertions · Generation of constrained random test stimuli · Deep understanding of UVM: structures, components, sequences, and configuration · Knowledge of UVM phasing, TLM, and factory concepts · Basic understanding of formal verification, FPGA-based prototyping, and emulation Hands-On Projects👨🏻💻: · Developed a class-based SystemVerilog testbench for a synchronous FIFO · Built a top-level UVM environment for a synchronous FIFO I extend my sincere gratitude to Eng. Kareem Waseem for his invaluable guidance and to Magdy Ahmed and Mustafa Ibrahim and Alaa Salah for their insightful assistance. #digitalverification #systemverilog #UVM #verification #FPGA #RTLdesign #functionalcoverage #assertions #SystemVerilogAssertions #randomtesting #constrainedrandom #verificationengineer #formalverification #hardwareverification