Arteris’ Post

The transition to a chiplet design paradigm will impact modern design flows, requiring optimization of the functional partitions among chiplets. The new design flows for chiplet-based systems should consider the potential for heterogeneous technology integration and manage the complexity of high-density die-to-die interconnects with an awareness of the possibilities and constraints offered by emergent fabrication and packaging technologies. I recently shared my thoughts on this with Semiconductor Engineering.

Cadence is proud to be a gold sponsor of the International Test Conference India 2024. Visit Cadence in booth #5 to learn how the Cadence Modus DFT Software Solution can reduce test time by up to 3X using its patented physically aware 2D Elastic Compression architecture without impacting fault coverage or chip size. More details about the conference - https://ow.ly/yO6l50SEPUz #Test #DFT #Cadence #Modus

Cadence is proud to be a gold sponsor of the International Test Conference India 2024. Visit Cadence in booth #5 to learn how the Cadence Modus DFT Software Solution can reduce test time by up to 3X using its patented physically aware 2D Elastic Compression architecture without impacting fault coverage or chip size. More details about the conference - https://ow.ly/Inka50SFoEC #Test #DFT #Cadence #Modus

The world of electronics design thrives on efficient tools that bridge the gap between concept and silicon. Virtuoso Digital Implementation is a powerful ally for mixed-signal designs, which integrate both analog and digital components. Learn about Virtuoso Digital Implementation's capabilities and explore how it can streamline your mixed-signal design workflow. https://ow.ly/WykO50SRsgB #virtuoso #digitalimplementation #Cadence #silicon

Register: https://bit.ly/4aN6k6E In this webinar learn about 3 key issues that engineers must overcome to sign off on high-speed PCB designs: serial link compliance (SerDes), power analysis, and DDR memory interface compliance. We will demonstrate how Cadence’s PCB design methodology, including Sigrity Aurora, Sigrity SystemSI, and Allegro technologies, empowers EEs to create successful products on time and on budget. #PCBdesign #engineer

Cadence Voltus users can see how to improve power network design in 3D ICs at this webinar, September 12, 10:00AM PT #SemiEDA https://lnkd.in/gGnsrWCs

👉🏼 The high data rates and miniature scale of high-speed electronics require very high signal and power integrity (SI/PI), with a very low risk of interference or noise. 👉🏼 Providing understanding of how to use CST Studio Suite for signal integrity/high speed technology and to set-up and run an electromagnetic simulation as well as integrating EDA workflow is the focus of our training class “CST Studio Suite – EDA / SI-PI” with Frank Demming-Janssen and Keran Wang in Münster on 14 – 15 May 2024.   >> First simulate, then fabricate << Using signal and power integrity simulation you can: ✔️ ensure the quality of signal transmission and reception on the PCB, ✔️ fix signal distortion, propagation delays, and jitter, ✔️ as well as monitor the design of the power distribution network (PDN) to ensure a stable and clean power supply, avoiding power noise and voltage drops.   More information and registration >> https://bit.ly/EDA-05-2024   #PCB #powerintegrity #circuitboard #circuitdesign #pcbdesign #powerintegrity #virtualtwin #signalintegrity #highspeedtechnology #simulation #eda

Now Available: Version 24.5.4 of the Modelithics Qorvo GaN Library. This release includes new models for Qorvo, Inc. QPD1035 and QPD1035L Discrete GaN-onSiC HEMTs. The QPD1035 and QPD1035L are 40-W devices with load pull validation of 4, 5, and 6 GHz and a max frequency of 6 GHz. Both models are non-linear models and include temperature scaling. Also available with this release are two new embedding models for TGF2977-SM (5W) and QPD1022 (10W) devices. This release is compatible with Keysight Technologies ADS 2022 - 2024 Update 2 and Cadence Design Systems AWR Design Environment 16 and 17.3+. Request FREE Access Today: https://lnkd.in/gBCs9hn #modelithics #qorvo #keysightads #cadenceawr #qorvogan #embeddingmodels

I’m exited to share that I have finally completed the design of “two stage – Miller compensated OTA using the effective gm/id methodology. This project was developed using cadence virtuso & ADT tools .under the supervision of the expert Dr.Hesham Omran. Project specs: Technology: 180 nm Supply Voltage: 1.8 V Static Gain Error: ≤ 0.05% CMRR @ DC: ≥ 74 dB Phase Margin: ≥ 70° OTA Current Consumption: ≤ 60 µA CMIR (High): ≥ 1 V CMIR (Low): ≤ 0.2 V Load: 5 pF Buffer Closed Loop Rise Time (10% to 90%): ≤ 70 ns Slew Rate (SR): 5 V/µ Taking on consideration the body effect of the mosfets which was very challenging in 180nm technology to achieve the CMIR high spec, so I tried as much as possible to be close to the specs requirements Special thanks to Dr: Hesham Omran & TA’s:Ahmed Ashraf ,Mahmoud Abdeltawab & Information Technology Institute (ITI) to give me this great opportunity to work on this project Here is a detailed design steps and results :  #AnalogDesign #electronics #amplifiers #circuitdesign #Analog #cadence #ITI #ElecronicsEngineering

I'm happy to announce that i have finished designing Two Stage Miller OTA in Information Technology Institute (ITI) under Supervision Dr. Hesham Omran , by using Cadence Simulator , ADT Sizing Assistant , work on GF180n Technology and using the gm/id methodology with the following required specs : Supply voltage : 1.8V Static gain error : <= 0.05% CMRR @ DC : >= 74dB Phase margin (avoid pole-zero doublets) : >= 70 deg OTA current consumption : <= 60uA CMIR – high : >= 0.8V CMIR – low : <= 0.2V Output swing : 0.2 – 1.6V Load : 5pF Buffer closed loop rise time (10% to 90%) : <= 70ns Slew rate (SR) : 𝟓𝑽/𝝁𝒔 Specs Achieved : Static gain error : = 0.035% CMRR @ DC : = 81dB Phase margin (avoid pole-zero doublets) : = 73.5 deg OTA current consumption : = 50uA CMIR – high : = 0.9 V CMIR – low : = 0 V Output swing : 0.8 pk-to-pk Load : 5pF Buffer closed loop rise time (10% to 90%) : = 32.25 ns Slew rate (SR) : 5.14 𝑽/𝝁𝒔 Area : 67 pm^2 The main benefit of the second stage is to improve the output swing and got a high open loop gain and Verr almost equal zero , we use a Compensation Cap to got the req_PM and req_SR , the resistance Rz will produce a zero we can put it at infinite by putting its value = 1/Gm2 (the trance conductance of the second stage ) or we can use it to cancel the Wp2 but the settle time will increase this actually what am did . and finally special thank to Eng.Zeyad Amr and Eng.Abdelrahman Mostafa for good explanation and helping us to understand the tradeoff . #AnalogElectronics #ElectronicsEngineering #LearningJourney #CircuitDesign #TechSkills #AnalogCircuits #AnalogDesign #gmOverID #ADT #Cadence