More Than Moore!! hashtag
#MTM.
The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics.
Much of this has been driven by a reduction in performance and power benefits from scaling below 10nm, along with the growing number of physics-related issues at the most advanced nodes, such as multiple types of noise, thermal effects and electromigration.
Three major changes are underway in this “More Than Moore” paradigm:
1. Heterogeneous integration using chiplets.
2. Big improvements in multi-chip performance.
3. Shifts by all the major foundries into advanced packaging.
Part of the growth of MTM means potentially that Moore’s Law is really coming to an end, and some people think that it’s already ended.
Regardless, it absolutely will end at some point, at least for many components in an SoC.
Industry have already started looking at alternatives to simply scaling based on Moore’s Law because it just doesn’t make sense anymore.”
Why choose multi-die?
[Multi-die approaches] are a great way to more specifically tailor the process technology to what that part of the system needs to do.
AMD has a great example of a multi-die solution.
multi-die is a way to optimize the cost and then optimize where you’re spending your effort.
Choose your node:
Initial implementations were largely homogeneous, but that has shifted over the last few years due to the slowdown in Moore’s Law and the splintering of end markets.
That, in turn, has opened numerous opportunities for semi-customized solutions based on multiple process choices.
Typically, RF and high-speed RF is done in older geometries like 0.18, which is a pretty good geometry still for sub-6 Gbps. Above 6 Gbps, we probably go to 55nm. Those are the best nodes for RF.
At the same time, if you’ve got a requirement for a lot of processing, you want to go on to deeper geometries like 28nm or maybe down into the finFET space.
And then t’s going to need a high-speed interface, and that in itself will determine what geometry you can use, as well.
There are a lot of competing requirements, and everybody wants a monolithic die where everything’s on one die because that’s generally the cheapest thing.
But inevitably, in a lot of cases we have to provide a two-chip solution or in some cases a three-chip solution. It comes down to the best tradeoff between process and between functions.
SiP evolving to chiplets:
Instead of taking multiple chips, we’re now talking chiplets.
We’ve always had hard and soft IP, which are the keys to driving SoCs. We now have this third version of IP called the chiplet, which has been built, manufactured and tested.
Today, it’s only being done by vertically integrated companies that design the chiplet and the chip that they’re sitting on.
Credit: https://lnkd.in/gPccPYMD
Source: Cadence
