Ethernovia’s Post

Hi LinkedIn Tribe😎, My team in#TESSOLVE#bangalore/Hyderbad looking for candidates with an experience of 2-12 yrs. 🚀#Physical Design (PD) 🚀#STA Engineer 🚀 #Physical Verification(PV) 🕑 Notice period: Immediate joiner/ 90 days Candidates share your resume to soundar.selvanagarajan@tessolve.com ✅ 🏅 How to Fix a Setup Violation 🏅 ⛹♀️ Multi-Cycle Path (MCP) 🚰This method has some similarities to pipelining. Similarly, we will let the combinational path finish in multiple cycles. 🚰The difference is we won’t add pipeline registers. Instead, we will capture the data at another capture clock edge This can be done in 2 ways: 🚰Use a control circuit to mask the 1st capture edge and allow another one. 🚰 Use a divided clock for the capture FF as shown in the diagram below 

Hi LinkedIn Tribe😎, My team in#TESSOLVE#bangalore/Hyderbad looking for candidates with an experience of 2.5-12 yrs. 🚀#Physical Design (PD) 🚀#STA Engineer 🚀 #Physical Verification(PV) 🕑 Notice period: Immediate joiner Candidates share your resume to soundar.selvanagarajan@tessolve.com ✅ 🏅 How to Fix a Setup Violation 🏅 ⛹♀️ Multi-Cycle Path (MCP) 🚰This method has some similarities to pipelining. Similarly, we will let the combinational path finish in multiple cycles. 🚰The difference is we won’t add pipeline registers. Instead, we will capture the data at another capture clock edge This can be done in 2 ways: 🚰Use a control circuit to mask the 1st capture edge and allow another one. 🚰 Use a divided clock for the capture FF as shown in the diagram below

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Hi LinkedIn Tribe😎, My team in #TESSOLVE #bangalore/Hyderbad looking for candidates with an experience of 2-12 yrs. in, 🚀#Physical Design (PD) 🚀#STA Engineer 🚀 #Physical Verification(PV) 🕑 Notice period: Immediate joiner/ 90 days Candidates share your resume to soundar.selvanagarajan@tessolve.com ✅ 🌞Let discussing about Interview Questions 🐠 1 .Let's take one scenario FF1, No combo logic Only take 2 cells Buffer and AND Gate AND gate 2nd pin connected to FF3 AND out pin going to FF2 ? 🦾Condition: FF 1 to FF2 +100 PS Margin FF3 to FF 2 -50 ps violating & FF 1 to FF3 75 +Ve slack (This I didn't understand) & You do have 25 PS delay buffers for hold Where will you Add ? 2. If you have 2 Flops FF 1 & FF2 In B/w only 2 cells are there ie; Buffer and AND Gate? To fix hold violation In which path you add a buffer ? 🦾Plz share Answers below Comment

We will share insights on assessing the skills of hardware engineers. Stay tuned for expert advice on optimizing your hiring process in the dynamic field of hardware engineering. #HardwareEngineering #TechRecruitment #SkillsAssessment #EngineeringTalent #YRecruiter

Hi LinkedIn Tribe😎, My team in#TESSOLVE#bangalore/Hyderbad looking for candidates with an experience of 2-12 yrs. 🚀#Physical Design (PD) 🚀#STA Engineer 🚀 #Physical Verification(PV) 🕑 Notice period: Immediate joiner/ 90 days Candidates share your resume to soundar.selvanagarajan@tessolve.com ✅ 🏝 𝗖𝗥𝗢𝗦𝗦𝗧𝗔𝗟𝗞 𝗜𝗡 𝗩𝗟𝗦𝗜 🏝 👉 𝐖𝐡𝐚𝐭 𝐢𝐬 𝐜𝐫𝐨𝐬𝐬𝐭𝐚𝐥𝐤? Undesirable electrical coupling between adjacent signals on a chip is called crosstalk. 👉 𝐇𝐨𝐰 𝐢𝐭 𝐨𝐜𝐜𝐮𝐫𝐬? The victim net picks up a portion of the aggressor net's signal due to capacitive and inductive coupling, leading to potential errors in data transmission or logic operations. 👉 𝐖𝐡𝐚𝐭 𝐚𝐫𝐞 𝐭𝐡𝐞 𝐞𝐟𝐟𝐞𝐜𝐭𝐬? 🔹𝕊𝕚𝕘𝕟𝕒𝕝 𝕕𝕚𝕤𝕥𝕠𝕣𝕥𝕚𝕠𝕟: The victim net's signal gets corrupted by the aggressor's interference. 🔹𝕋𝕚𝕞𝕚𝕟𝕘 𝕖𝕣𝕣𝕠𝕣𝕤: Increase the propagation delay of the victim net's signal, violating timing constraints and causing malfunctions. 🔹𝕀𝕟𝕔𝕣𝕖𝕒𝕤𝕖𝕕 𝕡𝕠𝕨𝕖𝕣 𝕔𝕠𝕟𝕤𝕦𝕞𝕡𝕥𝕚𝕠𝕟: The energy that gets lost due to crosstalk results in an increased power consumption of the chip. 👉 𝐓𝐞𝐜𝐡𝐧𝐢𝐪𝐮𝐞𝐬 𝐭𝐨 𝐦𝐢𝐭𝐢𝐠𝐚𝐭𝐞 𝐜𝐫𝐨𝐬𝐬𝐭𝐚𝐥𝐤: 1️⃣ 𝕃𝕒𝕪𝕠𝕦𝕥 𝕋𝕖𝕔𝕙𝕟𝕚𝕢𝕦𝕖𝕤: 🔹Increase spacing between signal lines 🔹Assign critical signals to top layers 🔹Route sensitive signals orthogonally 🔹Shielding 2️⃣ ℂ𝕚𝕣𝕔𝕦𝕚𝕥 𝕋𝕖𝕔𝕙𝕟𝕚𝕢𝕦𝕖𝕤: 🔹Lower slew rates 🔹Driver isolation 🔹Driver sizing 3️⃣ ℙ𝕣𝕠𝕔𝕖𝕤𝕤 𝕋𝕖𝕔𝕙𝕟𝕚𝕢𝕦𝕖𝕤: 🔹Low-k dielectric materials 🔹Substrate optimization The optimal choice of techniques depends on the specific design constraints, performance requirements, and available resources. Image source: https://lnkd.in/d8uxhEbC Source:pooja kumawat

Shout out to all #physicaldesigners and #designverificationengineers with experience range between 3 to 9 years willing to work on a world class product. You may inbox me your resumes here at LinkedIn. For any queries please feel free to write me here in the comment box. #physicaldesigners #PDEngineer #STA #PnR #clocktreeanalysis #PlacementRoute #Verificationengineer #Verilog #VHDL #Systemverilog #designverification #hiring

Hi LinkedIn Tribe😎, My team in#TESSOLVE#bangalore/Hyderbad looking for candidates with an experience of 3-12 yrs. 🚀#Physical Design (PD) 🚀#STA Engineer 🚀 #Physical Verification(PV) 🕑 Notice period: Immediate joiner Candidates share your resume to soundar.selvanagarajan@tessolve.com ✅ 🎏 Timing Library (.lib)(Part -1) 🏉  pin(CK) {     🥊 capacitance : 0.000380664 ;     🥊clock : true ;     🥊direction : input ;     🥊driver_waveform_rise : "driver_waveform_clockpin_rise" ;     🥊driver_waveform_fall : "driver_waveform_clockpin_fall" ;     🥊fall_capacitance : 0.000403988 ;     🥊input_voltage : clockpin ;     🥊max_transition : 0.250000 ;     🥊related_ground_pin : VSS ;     🥊related_power_pin : VDD ;     🥊rise_capacitance : 0.000380004 ; 🎍 internal_power() {      🥊 related_pg_pin : "W" ;       🥊when : "!CK&!R&!SE&!SI" ; 🎍library(xxpe_sc_xxt_mbslk_xxxxpg_nominal_min_xxxxxx_125c) {   delay_model : table_lookup ;   revision : "111";   🥊library_features(report_delay_calculation, report_power_calculation, report_noise_calculation);   🥊time_unit : 1ns ;    🥊voltage_unit : 1V ;    🥊current_unit : 1mA ;    🥊capacitive_load_unit(1, pf);   🥊pulling_resistance_unit : 1kohm ;    🥊leakage_power_unit : 1uW ;    🥊input_threshold_pct_fall : 50 ;    🥊input_threshold_pct_rise : 50 ;    🥊output_threshold_pct_fall : 50 ;    🥊output_threshold_pct_rise : 50 ;    🥊slew_derate_from_library : 0.5 ;    🥊slew_lower_threshold_pct_fall : 30 ;    🥊slew_lower_threshold_pct_rise : 30 ;    🥊slew_upper_threshold_pct_fall : 70 ;    🥊slew_upper_threshold_pct_rise : 70 ;    🥊nom_process : 1 ;    🥊nom_temperature : 125 ;    🥊nom_voltage : 0.705 ;    🥊default_cell_leakage_power : 0 ;    🥊default_fanout_load : 1 ;    🥊default_inout_pin_cap : 1 ;    🥊default_input_pin_cap : 1 ;    🥊default_leakage_power_density : 0 ;    🥊default_max_transition : 0.501877 ;    🥊default_output_pin_cap : 0 ;    📢 operating_conditions(ff_125c) {    🥊process : 1 ;    🥊temperature : 125 ;   🥊 voltage : 0.705 ;   }  📢default_operating_conditions : ffv_125c ;  🥊input_voltage(clockpin) {   🥊 vil : 0 ;   🥊 vih : 0.705 ;   🥊 vimin : 0 ;    🥊vimax : 0.705 ;   }  🔨 sensitization(sensitization_10pins) {   🥊 pin_names(pin_0, pin_1, pin_2, pin_3, pin_4, pin_5, pin_6, pin_7, pin_8, pin_9);   🥊vector(0, "0 0 0 0 0 0 0 0 0 0");   🥊vector(1, "0 0 0 0 0 0 0 0 0 1");   🥊vector(2, "0 0 0 0 0 0 0 0 1 0"); 🔨lu_table_template() {    🥊variable_1 : input_noise_height ;   🥊 variable_2 : input_noise_width ;    🥊variable_3 : total_output_net_capacitance ;    🥊variable_4 : time ;    🥊index_4("1, 2, 3, 4, 5"); 🔨cell(SDFF) {    🥊sensitization_master : sensitization_7pins ;    🥊pin_name_map(CK, D0, D1, SE, SI, Q0, Q1);   🥊area : 0.036544 ;   🥊 cell_footprint : SDFF ;   🔨leakage_power() {      🥊related_pg_pin : "VDD" ;      🥊when : "!CK&!D0&!D1&!SE&!SI" ;      🥊value : "0.0445957" ;    }

Dear Connections, Cientra is #immediatelyhiring #design_verification  #Noidalocation #Exp: #2+yrs #NoticePeriod: #immediatejoiners please share your resumes to sai.shrashti1264@cientra.com #systemverilog #verilog #uvm #socverification #ipverification #verificationengineer #asicverification