Nanjuraj R’s Post

Hi Connections, #SpanIdea System Immediately Hiring, #FPGA  Design Engineer #Experience:Strictly 2-10 Yrs Location: Hyderabad PFA JD: Hi Connections, #SpanIdea System Immediately Hiring, #RTL Design Engineer #Experience:Strictly 2-8Yrs Location: Hyderabad PFA JD: Setup ASIC QA flows for RTL design quality checks. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. Advocate clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers. Checking the flow errors, design errors & violations and reviewing the reports. Debugging CDC, RDC issues and propose the RTL fixes. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. Flows or Design porting to different technology libraries. Generating RAMs based on targeted memory compilers and integrating with the RTL. Familiar with the functional verification simulations. Interested PPL Share your Resume to vandanab@spanidea.com or Contact me - 7975278067

🎉 Thrilled to share that I have officially completed my VLSI RTL Design and Verification course at Maven Silicon, Bangalore—a leading name in VLSI training! This intense, hands-on journey has not only sharpened my technical skills but also fueled my passion for the semiconductor industry. From foundational RTL design principles to mastering advanced System Verilog techniques and UVM methodology, this course gave me the opportunity to work on cutting-edge projects and tackle real-world scenarios. Some of my favourite projects included DRAM and 1x3 Router design, as well as AHB to APB bridge protocol verification, each enhancing my understanding of digital logic, design synthesis, and verification environments. Throughout the program, I gained valuable skills in debugging, testbench architecture, and functional coverage, which are essential to ensuring the quality and reliability of today’s complex digital systems. I also gained experience using industry-standard tools like VCS and Questasim for verification, making me more confident and prepared for the challenges in VLSI. A heartfelt thanks to the exceptional mentors and the Maven Silicon team for their support and guidance. This experience has been instrumental in shaping my expertise, and I’m excited to bring these skills into the field, contribute to future innovations, and make a meaningful impact in VLSI design! #ProudMoment #VLSI #RTLDesign #SystemVerilog #UVM #DigitalDesign #Semiconductors #MavenSilicon #Bengaluru #Innovation #LearningJourney #CareerGrowth

Hiring Design Verification Engineer Years of experience: 6 to 15 years Area of expertise: System Verilog and UVM, PCIe, Ethernet Positions: Senior Project Engineer's to Tech Lead Locations: Bangalore, Hyderabad and Ahmedabad #bengaluru #bengalurujobs #hyderabad #hyderabadjobs #ahmedabad · BE/ B.Tech/ Master degree in Electrical Engineering or Computer Science · 6+ years of experience in pre-silicon RTL Verification /IP Verification / SOC verification · Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas 1. System-on-a-chip verification with multiple CPUs and fixed function units with AXI or NOC interconnects 2. Verification of embedded CPUs such as ARM, Tensilica, MIPS CPUs and interconnect subsystem through C/Assembly language tests 3. Verification of industry standard serial interfaces such as MIPI, USB, PCIe using industry standard VIP components. 4. Ethernet Packet Processors, buffer managers, DMA engines etc.... 5. PHY layer verification of serial interfaces such as Ethernet, PCIe, USB etc. 6. Solid Linux environment skills including the use of Perl, Python or TCL to write/debug CAD tool scripts. #rtlverification #socverification #ipverification #presiliconverification #uvm #systemverilog #pcie #ethernet #arm #rtl #buffer #dma #mips #presilicon #chipverification #designverification

The Importance of Targeting a Specific Role in VLSI in 2025 🎯 I. Introduction A. Brief overview of the VLSI industry and its vastness 🌍 B. Importance of understanding specific roles and requirements 🔎 II. Companies' Preference for Targeted Skills A. Post-COVID trend of companies preferring candidates with specific skills 📊 B. Long-term career implications of choosing a role 💼 III. Main Divisions of the VLSI Industry A. Frontend Design 1. RTL Design Engineer 🖥️ 2. Design Verification Engineer 🛠️ 3. Performance Verification Engineer 🚀 B. Backend Design 1. STA/Synthesis Engineer 🎛️ 2. Physical Design Engineer 🗺️ 3. Physical Verification Engineer 🕵️ 4. DFT Engineer 🔒 5. Post-Silicon Validation Engineer 🔬 IV. Skills and Qualifications for Design Roles A. Verilog, digital design, C programming, and STA basics 📐 B. Project ideas for design roles 💡 V. Skills and Qualifications for Design Verification Roles A. Verilog, SystemVerilog, UVM, object-oriented programming, digital design, C++ (OOP concepts), and debugging abilities 🐛 B. Project ideas for design verification roles 💻 VI. Skills and Qualifications for Backend Roles A. Understanding backend flow, CMOS circuits, digital design, and VLSI design concepts 💡 B. Project ideas for backend roles 🔧 VII. Essential Skills for All Roles A. Scripting languages like Python, Perl, and TCL 🐍 VIII. Conclusion A. Recap of the importance of targeting a specific role in VLSI ✅ B. Encouragement for continued learning and exploration of resources 📚 |------------------------------------------------------------------------------- Follow us @ LinkedIn 🌐 https://lnkd.in/g4JgVyrN Learn more at VLSI Job Seekers 📚 WhatsApp us at 9113835242 📱 Any questions please drop here 💬 If you need any topic explanation , comment below ⬇️

Hi Buddy😎 we are looking for physical design engineer with strong RTL2GDS skills.(location for #bangalore /#hyderabad /#noida ) Roles & Responsibilities defined below: 1. #sta / Synthesis (Static Timing Analysis): Perform static timing analysis to ensure the design meets the specified timing constraints. Work closely with the design team to identify and resolve timing issues. Optimize the design for performance and power efficiency. SDC constraints development & clean -up . 2. #pnr (#placement and #router ): Execute place and route activities to achieve optimal physical implementation of the ASIC. Collaborate with the physical design team to address floor planning, placement, and routing challenges. Drive physical optimization techniques for area, power, and performance. Should have descriptive knowledge on signoff & ECO generation. 3. #asic Design: Contribute to the overall ASIC design flow from RTL to GDSII. Work on complex design challenges and propose innovative solutions. Collaborate with cross-functional teams, including RTL designers and verification engineers. 4.#methodology and #tool Development: Stay abreast of the latest advancements in physical design methodologies and tools. Contribute to the development and improvement of physical design methodologies. #pnr #pv #innovación #job #emir #synthesis #tessolve

Hiring for #AMS Verification Engineers For #Bangalore Location, Any References would be Highly Appreciated. JOB Description: . Hands on Experience in Mixed Signal Design Verification . Strong knowledge in Circuit Analysis and connect rules. . Good Understanding in analog signals interface between analog and digital domain. . Experience in UVM based AMS Verification( UVM-MS testbench setup) . Experience in Analog Behavioral Model development (WREAL, Verilog-A, System Verilog) . Experience in Real Number Modelling. . Experience in AMS test plan/test development and debug closure. #AMSVerification #RnMModeling #WREAL #Verilog #SystemVerilog #MixedSignalDesign

🚀 Mass Hiring - RTL/Emulation/FPGA Validation 🚀 Positions :- 1. Zebu Emulation & Validation (5 - 15 Years) 2. Pro FPGA Validation Prototyping (7 - 15 Years) 3. Senior ASIC/SoC RTL Engineer /Lead/Managers (5 - 20 Years) Locations :- Bangalore, Chennai, Hyderabad, Kochi, Pune, Noida, Ahmedabad Notice Period :- Immediate Joiner / 30 Days Max 1. Zebu Emulation & Validation (JD) 1) A good understanding of architectural aspects and RTL code at IP/Sub-system/SoC level 2) A good understanding of verification methodologies including SV-UVM/C based environment, transactors etc 3) Experience in building emulation models from scratch 4) Knowledge of Arm CPU cores, protocols including PCIe, USB, Ethernet, AMBA, UART/SPI/I2C, DDR, flash memories and their usage in SoC environments is necessary 5) Emulation experience on Zebu/Veloce/Palladium, including compilation, test execution, debug, and performance. 6) Strong scripting skills including UNIX shell scripting, Perl, TCL etc 7) Support various emulation users 8) Must have worked in end-to-end Emulation of at least 1-2 SoC programs in Sub-system and chip level 2. Pro FPGA Validation Prototyping 1.     Good understanding of verification and validation fundamentals 2.     Solid understanding of FPGA platforms like HAPS, proFPGA etc 3.     Good understanding of ARM based IPs, subsystem and SOC 4.     Integrate daughter cards and bring them up with real world devices and testers 5.     Good understanding of SOC boot-flow 6.     Good debug skills 7.     Knowledge of this protocols will be plus, I2C, I3C, SPI, SPMI, USB, PCIe, UFS 3. Senior ASIC/SoC RTL Engineer /Lead/Managers 1)   Expertise in SoC/IP design 2)   Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog 3)   In depth knowledge on RTL quality checks (Lint, CDC) 4)   Knowledge of synthesis and low power is a plus 5)   Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) 6)   Good understanding of timing concepts 7)   Knowledge of one or more of the interface protocols    a.   PCIe    b.   DDR    c.   Ethernet    d.   I2C, UART, SPI 8)   Expertise in setting up and using tools like    a.   Spyglass Lint/CDC      b.   Synopsys DC    c.   Verdi/Xcellium 9)   Understanding of scripting languages like Make flow, Perl ,shell, python etc 10)   Understanding of processor architecture and/or ARM debug architecture is a plus 11)   Able to help and debug issues for multiple subsystems 12)   Able to create/review design documents for multiple subsystems 13)   Able to support physical design, verification, DFT and SW teams on design queries and reviews.     ⬇                         ⬇                         ⬇  If you are Interested : Submit Your resume here : ⬇   📧 Gokul@livecjobs.com      📞  8147070958 #RTL #Emulation #FPGAValidation #LiveConnections #WePlacepeopleFirst #livec  

The Importance of Targeting a Specific Role in VLSI in 2025 🎯 I. Introduction A. Brief overview of the VLSI industry and its vastness 🌍 B. Importance of understanding specific roles and requirements 🔎 II. Companies' Preference for Targeted Skills A. Post-COVID trend of companies preferring candidates with specific skills 📊 B. Long-term career implications of choosing a role 💼 III. Main Divisions of the VLSI Industry A. Frontend Design 1. RTL Design Engineer 🖥️ 2. Design Verification Engineer 🛠️ 3. Performance Verification Engineer 🚀 B. Backend Design 1. STA/Synthesis Engineer 🎛️ 2. Physical Design Engineer 🗺️ 3. Physical Verification Engineer 🕵️ 4. DFT Engineer 🔒 5. Post-Silicon Validation Engineer 🔬 IV. Skills and Qualifications for Design Roles A. Verilog, digital design, C programming, and STA basics 📐 B. Project ideas for design roles 💡 V. Skills and Qualifications for Design Verification Roles A. Verilog, SystemVerilog, UVM, object-oriented programming, digital design, C++ (OOP concepts), and debugging abilities 🐛 B. Project ideas for design verification roles 💻 VI. Skills and Qualifications for Backend Roles A. Understanding backend flow, CMOS circuits, digital design, and VLSI design concepts 💡 B. Project ideas for backend roles 🔧 VII. Essential Skills for All Roles A. Scripting languages like Python, Perl, and TCL 🐍 VIII. Conclusion A. Recap of the importance of targeting a specific role in VLSI ✅ B. Encouragement for continued learning and exploration of resources 📚 You can then expand each section with relevant information, examples, and insights. Let me know if you need further assistance! |---------------------------------------------------------------- Follow us @ LinkedIn 🌐 https://lnkd.in/eTytVaZJ Learn more at VLSI Job Seekers 📚 WhatsApp us at 9113835242 📱 Any questions please drop here 💬 If you need any topic, comment below ⬇️

Open Positions