Onkar Sanjay Mane’s Post

In VLSI digital design from RTL to GDS extraction there are so many steps involved. Not many of us are aware about this. So let's dive in into the different steps of digital design. 1. RTL code writing: It's the starting point. Based on the functional requirement of chip we need to write code. This can be done using Verilog or VHDL. 2. Functional Verification: It's important to ensure the written code covers all the functionality of design. So lot of simulation and test cases are run to make code errorless. 3. RTL Synthesis: Process of converting code to gate level design. This process generates the optimised design in terms of PPA. 4. Technology mapping: It's important to map the generated design to some technology node. So that's why technology mapping is done where gate level generated design is mapped to required tech node. 5. Layout design: Since gate level design is ready so now layout is designed for the same. Floorplan, routing, placement all should be done properly to avoid any issues later. 6. PV: PV is physical verification. Here designed layout is make sure to meet with design rules and tech node constraints. 7. GDS extraction: Now since layout is ready and verified thoroughly, so GDS can be extracted. GDS is binary file contains full chip information. Follow @mosgyan for more such informative content. #vlsijobs #vlsidesign #vlsitraining #vlsi #analogdesign #chip #chipdesign #backend #digitaldesign #digitalcommunication #electronics #engineering #floorplanning #intel #mosgyan #nvidia #physicaldesign #semiconductor #tsmc #gds #rtl #verilog #vhdl #pv #synthesis #rtldesign #layoutdesign #coding #modelling #digitaldesigner

Demystifying Synthesis in VLSI Design 🛠️ In the world of #VLSIDesign, synthesis is a critical step that translates high-level hardware descriptions (like Verilog or VHDL) into gate-level representations. 🔑 Key Points: Behavioral to Structural: Synthesis takes RTL code and transforms it into a netlist of logic gates, enabling your design to become real hardware. Optimization: It’s more than translation—it optimizes your design for power, performance, and area (PPA). Various constraints, like timing, area, and power budgets, drive this process. Timing Considerations: Tools check for timing violations (setup and hold time) and ensure the design can operate at the required frequency. Technology Mapping: The logic is mapped to the available cells in the target technology library (standard cells), ensuring compatibility with the manufacturing process. Sequential vs Combinational Logic: Combinational logic and sequential elements (like flip-flops and latches) are handled differently, ensuring proper functionality in different timing scenarios. Post-Synthesis Simulation: Once synthesis is complete, it’s crucial to verify the gate-level netlist to ensure functionality remains intact. 🔍 Final Thoughts: Synthesis is where design becomes reality. It’s the bridge between coding hardware and creating the actual chip. Mastering synthesis optimization is key to achieving the best possible design in terms of performance and power efficiency. 💡 If you’re a PD or RTL engineer, understanding synthesis and its intricacies can massively improve your design workflow and end results! #VLSI #PhysicalDesign #RTLDesign #Synthesis #ChipDesign #Semiconductors #Engineering #ASICDesign

Hello Connections 🚀 Excited to share my recent project: Design and Verification of a 4-bit Carry Skip Adder (CSA) in Verilog! 🖥️ As part of my continuous learning in the VLSI domain, I designed and successfully verified a 4-bit Carry Skip Adder, a crucial arithmetic component optimized for faster addition. By allowing carry propagation to “skip” over groups of bits, this adder strikes a balance between performance and complexity. It was a great learning experience in understanding the trade-offs between different adder architectures and optimizing circuit design. 💡 Key Highlights: Reduced carry propagation delay compared to a ripple-carry adder, making the CSA more efficient for medium-performance applications. Designed the adder to handle various test cases and edge conditions, ensuring accurate carry-out and sum generation. Gained deeper insights into high-speed arithmetic circuits and how advanced techniques can improve performance in digital systems. 🔧 Tools Used: Modelsim: Simulated the design, analyzed waveforms, and validated the functionality of the CSA. G-vim: Used this text editor for writing clean, efficient Verilog code. This project helped me improve my understanding of digital circuit design, and gave me a practical approach to working with adders. It also reinforced my skills in RTL design and design verification, both essential for developing complex digital systems like ASICs and FPGAs. GITHUB Link : https://lnkd.in/eBTXXTwv #VLSI #ASIC #DV #RTL #FPGA #Verilog #Modelsim #DigitalDesign #HardwareDesign #DesignVerification #EDA #UVM #SoC #Semiconductor #Gvim #AXI #SystemVerilog #FunctionalVerification #RTLDesign #EDAtools #FPGAdevelopment #ASICdesign

Hello Connections, ✨ Project Highlight: RTL Design, Synthesis, and Verification of Time of Day Clock ⏰ Excited to share my latest project where I designed, synthesized, and verified a Time-of-Day Clock using Verilog! 🔧 Key Highlights: RTL Design: Developed a register-transfer level (RTL) design for a digital clock that tracks hours, minutes, and seconds using synchronous sequential logic. Synthesized Design: Synthesized the RTL code to ensure hardware compatibility and readiness for FPGA deployment. Simulation: Conducted extensive simulations to verify the design’s functionality, including time progression, reset functionality, and optimized clock divider performance for faster verification. 🔩 Steps for Implementation: Divide the System Clock: Divided the system clock down to generate a 1 Hz clock for counting seconds. Second Counter: Implemented a counter to count from 0 to 59, reset to 0, and increment the minute counter. Minute Counter: Created a minute counter that counts from 0 to 59, then resets and increments the hour counter. Hour Counter: Designed the hour counter to count from 0 to 23 for a 24-hour clock. 💡 This project helped deepen my understanding of digital system design, clock division, and the complete RTL-to-synthesis flow, preparing me for more complex VLSI and digital projects. Looking forward to applying these skills to new projects!🚀 #FPGA #Verilog #RTLDesign #Synthesis #Simulation #HardwareVerification #DigitalDesign #ClockDivision #Vivado #VLSI #ECEprojects #ASIC

🌟synthesis stage in VLSI 🌟 Synthesis is a critical step for chip designers because it allows them to visualize how the design will appear after manufacture. "Synthesis is a process of converting a high-level of abstraction to a low-level of abstraction" synthesis=Translation+optimization+ mapping we do synthesis for 1) Converting RTL to basic logic gates 2) Mapping those gates to actual technology-dependent logic gates accessible in technology libraries 3) Optimizing the translated netlist while maintaining the designer's limitations. Goals of synthesis is 1) To get a gate-level netlist. 2) Inserting Clock gates. 3) Logic optimization. 4) Inserting DFT logic. 5) Logic Equivalence between RTL and Netlist should be maintained. Inputs required for synthesis. * High-Level Design Description (HDL) (Verilog, VHDL) & Design Exchange Format (DEF file) & Physical Library (LEF) & Timing Library (.lil): Unified Power Format (.upf): & Standard Design Constraints (.sdc) Outputs for synthesis: * Netlist output.SDC #vIsi #vIsijobs #vIsidesign #vIsitraining #vIsicourses #vIsifreshers #vIsijobseekers #lowpower #chipdesign #chips #semiconductor #semiconductorindustry #semiconductorjobs #semiconductormanufacturing #physicaldesign #designengineer #maven #mavensilicon #rvvIsi #cmos #digitalelectronics #banglorejobs #bangalore #electronics #electronicsengineering

One of the important aspect in Verifying a RTL design is to use Assertion Based Verification (ABV) techniques. Assertions are used as a check against a design. For VLSI, someone needs to provide equal emphasis to SystemVerilog Assertions (SVA) in addition to Verilog, SV, Digital Design, etc. Below are some of the advantages of using Assertions in both RTL design and Verification: [1] SVA has to be written by both RTL designers and Verification engineers. RTL assertions mostly deals with microarchitectural specification while verification engineers deals with interface and functionality based assertions. [2] SVA improves the Observability of the design and thereby reducing the overall debug effort. This can be achieved by inserting various check points within the specific areas of the design to check the effect of internal bug instead of waiting for the entire Testcase to complete and then to backtrace the signal to find out the bug. [3] SVA can be written at multiple places within the Testbench like interfaces, monitor, scoreboard and even using bind with the top module to improve the probability of catching bugs within the design. [4] SVA has the keyword called as “cover” which will make sure the assertions are covered and is also used as a key indicator to measure verification progress. [5] SVA reduces the time to bring up the code because a simple logic may became cumbersome while trying to implement with Verilog and hence it makes the code more readable. Property P1; @(posedge clk) abc |-> ##[1:2] cd; endproperty assert property (P1); [6] SVA has assertion directives like assume, expect and restrict apart from assert which can be used in coding several temporal assertion as per the requirement. [7] Assertions has the capability to capture specific scenarios to measure coverage which is a important parameter to close coverage. [8] Since assertions are by default always on, they are useful in tracking the Testcases faster in case of any error. #vlsi #asic #electronics #electricalengineering

🌟 synthesis stage in VLSI 🌟 Synthesis is a critical step for chip designers because it allows them to visualize how the design will appear after manufacture. "Synthesis is a process of converting a high-level of abstraction to a low-level of abstraction" synthesis=Translation+optimization+ mapping we do synthesis for 1)Converting RTL to basic logic gates 2)Mapping those gates to actual technology-dependent logic gates accessible in technology libraries 3)Optimizing the translated netlist while maintaining the designer’s limitations. Goals of synthesis is 1) To get a gate-level netlist. 2) Inserting Clock gates. 3) Logic optimization. 4) Inserting DFT logic. 5) Logic Equivalence between RTL and Netlist should be maintained. Inputs required for synthesis. 📌High-Level Design Description (HDL) (Verilog, VHDL) 📌Design Exchange Format (DEF file) 📌Physical Library (LEF) 📌Timing Library (.lib): 📌Unified Power Format (.upf): 📌Standard Design Constraints (.sdc) Outputs for synthesis: 📌Netlist 📌 output.SDC Can we do scan insertion while synthesis/before synthesis/after synthesis ? * During synthesis: This is the most common approach, as it allows the scan insertion tool to optimize the scan chains for performance and area. * Before synthesis: This approach is less common, but it can be used to improve the testability of the design before any optimizations are performed. *After synthesis: This approach is the least common, as it is the most disruptive to the design flow. However, it can be used to add scan to a design that was not originally designed for testability. In general, scan insertion during synthesis is the best approach for most designs. #Physicaldesign #VLSI #soc #asicflow #electronicsandcommunication #synthesisstage #chipdesign

💡 What is ASIC Design? Application-Specific Integrated Circuits (ASICs) are custom chips designed for a specific task or product, and they play a huge role in today’s technology. Here’s a soft and simple breakdown of the ASIC design flow: Concept & Specification 📝 Start with an idea! Define what the chip needs to do, its performance goals, power usage, and size. Design 💻 Write the functionality of the chip using a hardware description language like Verilog or VHDL. This part is where we define the logic of the chip. Synthesis 🔄 Convert the design code into actual logic gates that can be implemented in hardware. Think of it as turning abstract ideas into something physical! Floorplanning & Placement 🏗️ Organize where each component of the chip will go on the silicon to make the design efficient and fast. Verification 🔍 Ensure that the chip works as expected by simulating and testing the design before manufacturing. This step avoids costly mistakes later on! Tape-Out & Manufacturing 🏭 Once everything is ready and verified, the design is sent to a fab (fabrication facility) where it is manufactured into real silicon. Testing & Packaging 📦 After production, the chip is tested to ensure it works correctly and is then packaged for use in electronic devices. ASICs are everywhere—from your smartphone to space exploration tech. Each step in this process brings your design closer to becoming reality! #ASIC #ChipDesign #TechSimplified #Semiconductors #PhysicalDesign #DigitalDesign #CTS #RTLDESIGN

While modelling testbenches in verilog, we need to drive it at the negedge of clock while the RTL should be at the posedge of clock. This will ensure that there will not any race condition. But still there multiple issues with Verilog based testbenches. But in SystemVerilog there are multiple ways to ensure that there will be no race conditions. Some of the ways are discussed below: [1] Clocking Block: a. Clocking Block provides synchronization as well as direction of signals to the testbench. b. The default input skew is 1step which will ensure that the signal should be sampled at the end of previous time step and the output skew should be provided with a delay equivalent to clk-to-q which will ensure the outputs are driven correctly. c. Clocking Block execution should be in sync with assertion evaluation at the observed region. d. While accessing the signals in a clocking block, it should always be accessed with clockvar and not the signals directly. [2] Program Block: Program block acts as a separator b/w the DUT and the testbench which will ensure that the RTL is executed at the Active region and the Testbench is executed at the Reactive region. [3] Specify Block: It provides the timing checks and ensure that the inputs satisfy the timing constraints. [4] Event Regions in SV: a. Event scheduling at Active / NBA regions and Reactive / Re-NBA regions and avoiding the Inactive region. b. Evaluation of assertion at observed region and execution of pass / fail block at Reactive region. [5] Modport: a. Provides direction of DUT and Testbench. b. Provides direction of clocking block signals. [6] Adherence to coding guidelines: a. While modelling driver, use of nonblocking statements are needed. b. While modelling Combinational logic blocking statements are needed while for sequential logic, use of non blocking statements are needed. #vlsi #asic #electronics #engineering