Shriram S’ Post

🚀 Excited to share some SystemVerilog code for a D Flip-Flop! 🚀 Hey everyone! 👋 I've just posted some SystemVerilog code for a D Flip-Flop on EDA playground to get basic knowledge to write code in SystemVerilog. If you're interested in learning about digital design and Verification and hardware description languages, check it out here: https://lnkd.in/ej9GPkBd Feel free to clone, fork, or contribute to the code. Learning digital design concepts like flip-flops is crucial for understanding the foundation of computer architecture and digital systems. If you have any questions, suggestions, or just want to discuss digital design, drop a comment below! Let's learn together! 🌟 #SystemVerilog #DigitalDesign #Verilog #HardwareDescriptionLanguages #FlipFlop

🚀 Day 23 of #25daysRTLchallenge: Unveiling the Power of Virtual Interfaces! 🌐💻 Hey LinkedIn fam! A virtual interface in SystemVerilog serves as a pointer to an actual interface. It is particularly useful within classes, providing a connection point for accessing the signals in the interface through the virtual interface pointer. 🌟🔄 Purpose of Virtual Interfaces: System Verilog interfaces are static in nature, while classes are dynamic. Due to this distinction, directly declaring an interface within a class is not allowed. However, we can refer to or point to an interface using a virtual interface. Essentially, a virtual interface acts as a bridge between the static interface and dynamic class contexts. It was a day of unraveling the magic behind effective Virtual Interfaces. 💬💻 #RTLDesign #VirtualInterfaces #DigitalDesign

Hi folks, here I have posted my understanding of the 'bind' directive. The bind directive in System Verilog plays a pivotal role in enhancing modularity, flexibility, and code reusability. 🔹 What is the 'bind' Directive? The bind directive is used to associate an assertion module with a design module or interface. It provides the capability to bind specific or all instances of a module or interface to the assertion module seamlessly. #verificationengineer #vlsi #designengineer #semiconductor #SystemVerilog #Verilog #UVM #assertion #sva #bind Eda link: https://lnkd.in/gpaNAPGi

🚀 Exciting Update from #25daysRTLchallenge Day 24: TB Randomize! 🌐 Hey LinkedIn fam! 👋 Today marks Day 24 of the #25daysRTLchallenge, and i am diving into the fascinating world of SV randomize function. 🎲✨ SV Randomize function is a game-changer in the realm of System Verilog, adding a dynamic twist to our RTL designs. It's all about injecting randomness into our simulations to uncover potential corner cases and enhance the robustness of our designs, randomize() function can accept any number of variables which have to be randomized as an arguments.  This function returns true if randomization was successful else false.  User can also provide inline constraints to control range of random values. As engineers, embracing SV Randomize allows us to simulate real-world scenarios, pushing our RTL code to its limits and ensuring it stands strong in unpredictable conditions. It's the secret sauce for robust and reliable designs! 🛠️🌐 I'm loving the journey through the #25daysRTLchallenge, and SV Randomize has been a highlight for me. How about you? Share your thoughts, experiences, or any cool insights! Let's keep the conversation going and learn from each other. 🤝💬 #SystemVerilog #RTLDesign #SVRandomization #LearningJourney 🚀🔧

Hello Everyone! I am here to share Cache Design in two languages: System Verilog and SystemC. SystemC is a C++ class library. I have tried implementing a Direct-mapped cache controller with four states implemented as a finite state machine. viz. idle, compare, allocate, and write_through. I request all the SystemC engineers to have a look at the cache design and provide feedback. This could help me strengthen my skills on SystemC. Here are the codes: SystemC: https://lnkd.in/gGWVSuqi System Verilog: https://lnkd.in/gcCKnQfm #SystemVerilog #SystemC #CacheDesign #ComputerArchitecture

🔍 Exploring D-flipflop UVM Verification 🚀 Excited to share a snippet of my recent work in Electronic Design Automation (EDA)! 🔧 Here's a peek into the UVM verification environment I've developed for a D-flipflop design. 🌐 EDA Playground Code : https://lnkd.in/gQPhbS_Q 👨💻 Leveraging UVM methodology ensures robust verification, validating functionality and performance metrics. 📈 Let's connect if you're into EDA or Verification—would love to discuss more! 🌟 #ElectronicDesign #Verification #EDA #UVM #SystemVerilog #verilog #Engineering #semiconductor

In the labyrinthine realm of digital design, the development and simulation of a fully connected layer in Verilog were adeptly executed using EDA Playground. This online sanctum afforded an effortless medium to craft, validate, and execute HDL code sans local installations. With its diverse array of simulators, the intricacies of the design were swiftly tested and verified, demonstrating flawless functionality. EDA Playground's sophisticated features harmonized the workflow, rendering the HDL development process remarkably efficient. Embrace the enlightenment that EDA Playground bestows upon your digital design endeavors.

Hi folks, I hope this message finds you well. I am reaching out because I have a question regarding argument passing in Verilog. Given your expertise in this area, I like to hear your valuable insights!!! The question is why can't we pass arguments in function definition while defining width for the variable using function ? Here is the code, module width_finding;  int a = 3;  int b = 3;  reg[f1(a,b):f2(a,b)] c;  initial begin   c = 5;   #10   $display("c = %0d",c);  end  function int f1(int a, int b);   return a+b;  endfunction  function int f2(int a, int b);   return a-b;  endfunction endmodule I have also attached the EDA link for your reference https://lnkd.in/ghrr4Y-n Thank you. #verificationengineer #vlsi #designengineer #verilog #semiconductorindustry

🚀 #RTLChallenge Day 3: Unveiling the Magic of Edge Detection! 🌐💡 Hello LinkedIn enthusiasts! 👋 Day 3 of #RTLChallenge had us deep into defining edge detection, the art of spotting signal shifts – from low to high (rising edge) or high to low (falling edge). It's the pulse of responsiveness in digital systems. 🕵️♂️✨ 🎯 What's Edge Detection? In a nutshell, edge detection is the art of spotting signal shifts – from low to high (rising edge) or high to low (falling edge). It's the pulse of responsiveness in digital systems. 🕵️♂️✨ 💻 Design Dive: With edge detection defined, today's mission was a design dive into crafting Verilog magic. I explored raising and falling edge detection, sculpting code to capture those crucial transitions in our signals. 💻🔍 🔍 Verification Journey: After the design, verification involved simulations, testing, and waveform analysis, ensuring our detector is poised to catch those edges with precision. 🧪🔍 📊 Learning and Growing: The journey isn't just about code; it's about understanding the intricacies of edge detection, juggling parameters, and honing our design instincts. Each line of code is a step forward in this learning adventure. 📚💪 Excited for the discoveries ahead! Stay curious, keep coding, and may your edge detectors be as sharp as ever! 🚀🔧 #DigitalDesign #FPGA #Verilog #vlsi