Good opportunity
#Qualcomm is hiring Design Verification engineers for SOC Verification team between the experience range 3 to 8 years of experience for HYD location. Interested and eligible candidates can send their resume to me at hmarryka@qti.qualcomm.com to apply. Note: veloce , SOC background adds advantage.
Good opportunity
We are hiring SoC Emulation Engineers with 5+ years of experience at NXP, India. This is an excellent opportunity to work on cutting edge Software defined vehicle & IIoT products right from architecture definition to customer deployment covering entire product development lifecycle. If you are interested in enabling shift left design with advanced Emulation testbenches and HW assisted Verification, pls share your resume at gauravjain.jain@nxp.com Looking forward to seeing profiles from best in industry !!
Talent Acquisition Specialist - Analog/MS/RF IC Design at microTECH global Talent Pvt. Ltd.
For all the Digital Verification professionals, if you are contemplating on a career move or progression or even advise on market insights, then look no further, book a call with Saphron Kellett- Morris and clear your path!
I'm hiring Digital Verification Engineers! 🌟 If you're driven, detail-oriented, and ready to work on cutting-edge projects, we want to meet you. 🛠️💡 This is your opportunity to grow your career with a dynamic and forward-thinking company. Reach out to me today for more details and to discuss how you can contribute to our success! 📲 #WeAreHiring #DigitalVerification #EngineeringCareers #OpportunityKnocks
Hiring Formal Verification Engineers for Palo Alto, CA. Local candidates for a W2 hourly Long-term projects. Know anyone who might be interested? #FormalVerification #FormalVerificationEngineer #FormalVerificationExpert #DesignVerification #DesignVerificationEngineer #UVMVerification #PCIEVerification #CPUVerification #GPUVerification #CXL #Supercomputer #FunctionalVerification #AI #Network-on-Chip #ArtificialIntelligence #ASIC #FPGA #Monitors #Drivers #Scoreboards #Sequences #Assertions #IPs #Subsystem #Highspeed #SOC #VIP #PCIE #PHY #Processor #AR #VR #MachineLearning #Ethernet #prototyping #constrainedrandomtest #testbench #Siliconbringup #cpusubsystemlevel #AMBA #DDR #Emulation #postsilicondebug
Hiring Formal Verification Engineers for Palo Alto, CA. Local candidates for a W2 hourly Long-term projects. Know anyone who might be interested? #FormalVerification #FormalVerificationEngineer #FormalVerificationExpert #DesignVerification #DesignVerificationEngineer #UVMVerification #PCIEVerification #CPUVerification #GPUVerification #CXL #Supercomputer #FunctionalVerification #AI #Network-on-Chip #ArtificialIntelligence #ASIC #FPGA #Monitors #Drivers #Scoreboards #Sequences #Assertions #IPs #Subsystem #Highspeed #SOC #VIP #PCIE #PHY #Processor #AR #VR #MachineLearning #Ethernet #prototyping #constrainedrandomtest #testbench #Siliconbringup #cpusubsystemlevel #AMBA #DDR #Emulation #postsilicondebug
Hiring Formal Verification Engineers for Palo Alto, CA. Local candidates for a W2 hourly Long-term projects. Know anyone who might be interested? #FormalVerification #FormalVerificationEngineer #FormalVerificationExpert #DesignVerification #DesignVerificationEngineer #UVMVerification #PCIEVerification #CPUVerification #GPUVerification #CXL #Supercomputer #FunctionalVerification #AI #Network-on-Chip #ArtificialIntelligence #ASIC #FPGA #Monitors #Drivers #Scoreboards #Sequences #Assertions #IPs #Subsystem #Highspeed #SOC #VIP #PCIE #PHY #Processor #AR #VR #MachineLearning #Ethernet #prototyping #constrainedrandomtest #testbench #Siliconbringup #cpusubsystemlevel #AMBA #DDR #Emulation #postsilicondebug
Hiring Formal Verification Engineers for Palo Alto, CA. Local candidates for a W2 hourly Long-term projects. Know anyone who might be interested? #FormalVerification #FormalVerificationEngineer #FormalVerificationExpert #DesignVerification #DesignVerificationEngineer #UVMVerification #PCIEVerification #CPUVerification #GPUVerification #CXL #Supercomputer #FunctionalVerification #AI #Network-on-Chip #ArtificialIntelligence #ASIC #FPGA #Monitors #Drivers #Scoreboards #Sequences #Assertions #IPs #Subsystem #Highspeed #SOC #VIP #PCIE #PHY #Processor #AR #VR #MachineLearning #Ethernet #prototyping #constrainedrandomtest #testbench #Siliconbringup #cpusubsystemlevel #AMBA #DDR #Emulation #postsilicondebug
Hiring Formal Verification Engineers for Palo Alto, CA. Local candidates for a W2 hourly Long-term projects. Know anyone who might be interested? #FormalVerification #FormalVerificationEngineer #FormalVerificationExpert #DesignVerification #DesignVerificationEngineer #UVMVerification #PCIEVerification #CPUVerification #GPUVerification #CXL #Supercomputer #FunctionalVerification #AI #Network-on-Chip #ArtificialIntelligence #ASIC #FPGA #Monitors #Drivers #Scoreboards #Sequences #Assertions #IPs #Subsystem #Highspeed #SOC #VIP #PCIE #PHY #Processor #AR #VR #MachineLearning #Ethernet #prototyping #constrainedrandomtest #testbench #Siliconbringup #cpusubsystemlevel #AMBA #DDR #Emulation #postsilicondebug
