Stage 4 Solutions’ Post

🚀 Video Course Alert: Mastering GLS and Verification Techniques! 👨💻 What You'll Learn: Join our comprehensive video course designed for engineers and verification specialists! This course covers everything from the Basics of Gate-Level Simulations (GLS) to advanced topics such as Formal and Assertion-Based Verification. Dive deep into: - Dynamic Verification & Formal Verification Techniques - In-depth GLS Workflows and Execution Strategies - Handling Complex Scenarios like Non-Resettable Flops and Power-Aware Simulations - Challenges and Performance Tips for Effective GLS 🔍 Why This Course? Whether you're a beginner aiming to get up to speed or a seasoned professional looking to improve your skills, this course offers practical insights and real-world applications. Learn to identify and tackle specific bugs only found in GLS, manage zero-delay problems, and understand the critical SDF format. 🎯 Who Should Enroll? Ideal for ASIC, FPGA, and design verification engineers looking to enhance their verification skillset and deliver flawless designs. ✅ Key Features: Interactive video lessons with real-world case studies Access to a community of experts and peers for discussion and doubt-clearance Certificate of Completion 📅 Ready to Sign Up? Contact to book - https://lnkd.in/gVpirNhG #GLS #Verification #FPGA #ASIC #DesignVerification #Engineering #OnlineCourse #ProfessionalDevelopment

To all those that are impacted by the Best Biy restructuring.

My Arteris colleague Insaf Meliane wrote a great article on "Navigating the Hardware-Software Interface in Chip Design." Register-transfer-level (RTL) verification is a critical component of successful chip design and Insaf describes how to design the hardware-software interface, how to deal with "bytes enables" in RTL verification and how to automate the HSI design process across the entire dev team. "The hardware-software interface (HSI) holds an important role in chip design, bridging the physical hardware and its software counterpart. It provides integration and performance optimization in complex system-on-chip (SoC) designs. However, issues can still arise with compatibility, timing, synchronization, testing, debugging, performance optimization, reliability, and power management. Hardware and software engineers seek to balance HSI challenges and requirements. Engineering groups have differing terminologies, though, adding another level of complexity to the project. Consequently, each group of engineers has their own unique areas of concern." Also, you can find more on the never-aging topic in "System-on-Chip Integration Complexity And Hardware/Software Contracts" at https://bit.ly/3QkzrF5. #Arteris #SoCIntegrationAutomation #SystemOnChip #Semiconductor https://bit.ly/3vY5Z0R

Dear Keysight Technologies, please don't 🙅♀️lay off anybody at Synopsys Optical Solutions Group (formerly RSoft Design Group) / Synopsys Optical Solutions. Not 1 person. They're magical 🧙♂️ superstars and we need all of them. A few days ago, news broke about  Synopsys' optics 🔦📸 stuff getting sold to Keysight, likely to let  the Synopsys takeover of Ansys  happen  without it getting stopped 🛑 by those annoying (j/k)  antitrust laws. I learned the news 📰 from Julius Muschaweck's post and was 1 of the nerds 🤓 that wrote the FTC about why if ALL THE OPTICALS BELONG TO SYNOPSYS  would be scary 😱 -- thanks to Max Henkart's public pleas to other optical engineers  to join his letter-writing 📩 efforts. This may be great news! BUT one thing I worry 😬 about -- is the prospect of losing any of the  critically valuable  knowledge 🧠 and people  to layoffs/restructuring. So Keysight,  in case you aren't aware  (but I really hope you are) optical simulations and the software associated is more like an artform 🎨 than a TI-89 calculator. 📲 It takes years 🗓️🗓️🗓️ of working with it to know how to best make it fit real-world 🌎 results. It takes even more years of experience to guide 👨🏫 others and explain the deeper levels of its functioning.  It isn't all completely explained in a manual 📖 somewhere. All the pros 😎🤩😏🥸😇 at Synopsys Optical Solutions Group are important, integral parts of the tools 🪛🛠️ you'll be selling. Please keep every precious one! #opticalengineering #simulations #optics #illumination #imaging #lighttools #codev #lucidshape #zemax #speos #lighting #ansys #synopsys #keysight

𝑭𝒓𝒆𝒒𝒖𝒆𝒏𝒕 𝒎𝒊𝒔𝒕𝒂𝒌𝒆 𝒗𝒆𝒓𝒊𝒇𝒊𝒄𝒂𝒕𝒊𝒐𝒏 𝒆𝒏𝒈𝒊𝒏𝒆𝒆𝒓𝒔 𝒎𝒂𝒌𝒆 is not 𝐢𝐧𝐬𝐢𝐬𝐭𝐢𝐧𝐠 on having their test plan reviewed. In theory, the architect should approve every verification plan. However, this often doesn't happen for many reasons. The most common one is an architect's lack of time. Another reason is that the verification engineer is "trusted" to have covered everything relevant. This approach can lead to severe problems down the road, such as realizing you didn't verify that one clear-on-read register that buried somewhere deep in the RTL. I strongly advise all verification engineers I work with to insist on having their test plan reviewed and approved. If this is not possible, raise a flag and say that it may lead to problems later on. #verification #verificationengineer #testplan #verificationplan #success #persistence

#Fundamentalsofverification As Designs are getting complex day-by-day, design-by-design and product-by-product, Verification also became a challenging task. These are different flows, methodologies and practices across industry but intention is same i.e. "Confidence of Zero defect design". To achieve it, fundamentals should be clear and deeply understood.. and it's not an easy task. One who is aspiring to be a Verification Expert, should have these technical knowhow -- 1. Testbench Architecture: To generate stimulus and observe the outputs. 2. Design understanding: Either IP or Integrated subsystem or Complete SoC or Chiplet 3. Measurement criteria for Design correctness: Functional coverage, Code coverage, Assertion coverage, Protocol checks coverage etc.. Here at #allaboutverification, we are trying to help aspiring Verification experts to redefine the learning curve or refresh the concepts.

𝙑𝙀𝙍𝙄𝙁𝙄𝘾𝘼𝙏𝙄𝙊𝙉 𝘿𝙄𝘼𝙍𝙄𝙀𝙎 #1 📖 📒 📓 I asked Anja Planić, one of our verification team leaders here at Vtool - Smart Verification, what part of IP verification she loves the most. "𝑻𝒉𝒆 𝒎𝒐𝒔𝒕 𝒊𝒏𝒕𝒆𝒓𝒆𝒔𝒕𝒊𝒏𝒈 𝒑𝒂𝒓𝒕 𝒇𝒐𝒓 𝒎𝒆 𝒊𝒔 𝒕𝒉𝒆 𝒄𝒓𝒆𝒂𝒕𝒊𝒗𝒊𝒕𝒚 𝒊𝒏 𝒊𝒎𝒑𝒍𝒆𝒎𝒆𝒏𝒕𝒊𝒏𝒈 𝒒𝒖𝒂𝒍𝒊𝒕𝒚 𝒄𝒐𝒅𝒆 𝒂𝒏𝒅 𝒕𝒉𝒆 𝒑𝒐𝒘𝒆𝒓 𝒐𝒇 𝒊𝒕𝒔 𝒓𝒆𝒖𝒔𝒂𝒃𝒊𝒍𝒊𝒕𝒚 𝒇𝒐𝒓 𝒕𝒉𝒆 𝒑𝒂𝒓𝒕𝒊𝒄𝒖𝒍𝒂𝒓 𝑰𝑷 𝒊𝒏 𝒕𝒉𝒆 𝒔𝒚𝒔𝒕𝒆𝒎𝒔. 𝑽𝒆𝒓𝒊𝒇𝒚𝒊𝒏𝒈 𝒂𝒏 𝑰𝑷 𝒈𝒊𝒗𝒆𝒔 𝒂𝒏 𝒆𝒏𝒈𝒊𝒏𝒆𝒆𝒓 𝒂 𝒎𝒐𝒓𝒆 𝒅𝒆𝒕𝒂𝒊𝒍𝒆𝒅 𝒆𝒙𝒑𝒍𝒐𝒓𝒂𝒕𝒊𝒐𝒏 𝒂𝒏𝒅 𝒂 𝒇𝒐𝒄𝒖𝒔 𝒐𝒏 𝒆𝒗𝒆𝒓𝒚 𝒅𝒆𝒕𝒂𝒊𝒍, 𝒘𝒉𝒊𝒄𝒉 𝒄𝒂𝒏 𝒈𝒓𝒆𝒂𝒕𝒍𝒚 𝒔𝒊𝒎𝒑𝒍𝒊𝒇𝒚 𝒕𝒉𝒆 𝒑𝒓𝒐𝒄𝒆𝒔𝒔 𝒐𝒇 𝒗𝒆𝒓𝒊𝒇𝒚𝒊𝒏𝒈 𝒄𝒐𝒎𝒑𝒍𝒆𝒙 𝒅𝒆𝒔𝒊𝒈𝒏𝒔 𝒖𝒏𝒅𝒆𝒓 𝒕𝒆𝒔𝒕." Stay tuned for more stories to come. #verificationengineer #diaries #verification #bestjobever #stories ---------------------------------------- In this series, I am asking verification engineers about various aspects of their jobs. My hope is that their stories will inspire more people to truly appreciate how the job of verification engineer is interesting, challenging, and at the end of the day, very fulfilling.

Exciting news - today we are sharing two breakthrough formal-based capabilities for high-level verification of C++ for hardware design: 1) formal property checking 2) formal reachability analysis. Designed to be used with our Catapult software for high-level synthesis and verification, Catapult formal tools uniquely bring known and trusted formal verification methods from the RTL world to high-level design. These have been developed jointly with partners and are actively in production use. “Catapult Formal tools are elevating best-in-class verification and design methods into High-Level Design,” said MO Movahed, our vice president and general manager for High-Level Design, Verification and Power. “By delivering formal methods to C++ verification, we are enabling leading-edge semiconductor teams to take full advantage of High-Level Synthesis and Verification’s power.” Let's dive in: 👇 » Catapult Formal Assert software delivers untimed C++ property checking to high-level verification. Designers can now use formal methods to prove that a high-level design representation conforms to a specification. Catapult Formal Assert proves whether a specific property, such as a value range, or specific signal values, can or cannot occur. » Catapult Formal CoverCheck is the formal complement to Catapult™ Coverage software, Siemens' simulation-based solution for metrics-driven verification of C++ and SystemC HLS design source. Catapult Formal CoverCheck performs "reachability analysis" on coverage holes and generates a waiver for those items formally proven to be unreachable. Together these two tools help users readily and efficiently achieve coverage closure on their HLS design source. Need more details? Check the comments for the link to our newsroom. #EDA #ElectronicDesignAutomation #News

Freshly released video on our #YouTube channel: Systems Engineering Part-2👇   Our Systems Engineering Team talks about model based systems engineering (MBSE), validation and verification (V&V) and suggestions for future systems engineers. In the Tech Talks series, we share the details of mobility technologies with our experts. Join us in this series and stay tuned for the upcoming videos!   👉🏼 https://lnkd.in/eGHDfM2z   #systemsengineering #mbse #modelbasedsystemsengineering #validation #verification #futuresystemsengineers #FeelEVolution

We're excited to announce that our CEO, Ashish Darbari, recently spoke with Semiconductor Engineering about the critical importance of formal verification in today's semiconductor market. In this enlightening conversation, Ashish discusses why formal methods are increasingly required to detect #deadlocks, #security holes, and #Xprop concerns in mission-critical, safety-critical, and #AI designs. He also looks at how these improvements will influence the future of #chiplets. For nearly two decades, #formalverification was viewed sceptically due to its perceived complexity and limited breadth, with many deeming it only fit for niche #bugfinding. However, the landscape has significantly changed. Formal is now widely regarded as robust and efficient, making it important for complete design verification. Watch the full interview here: https://lnkd.in/gsP872Un #Iloveformal #formalverification #engineering #futuretrends #semiconductorindustry