Exciting News! Vitesse Systems' CTO, Clency Lee Yow, will be the keynote speaker at the upcoming IEEE WAMS Conference next week. Clency will be shedding light on how Vitesse leverages its cutting-edge design, manufacturing, and test capabilities to deliver innovative antenna solutions for space, air, and ground applications. Join us as Clency delves into fascinating case studies, showcasing our Multi-Band Feeds, large feed clusters, patented reflector antennas, and more, all backed by our in-house manufacturing and testing prowess. Don't miss this insightful session! #VitesseSystems #IEEE #WAMSConference #AntennaSolutions #KeynoteSpeaker 🚀🛰️
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Jagmeet Singh's Digital Clock Marvel at RTRA! ⏰🔧 We're thrilled to announce a remarkable achievement from within our RTRA community! 🚀 Our talented student, Jagmeet Singh, has engineered something truly special – a digital clock that not only tells the time but does so with accurate precision! Clocking In Innovation: Jagmeet's ingenuity shines as he successfully crafted a digital clock using a microcontroller and servo motors. The result? A sleek timepiece that not only showcases his technical prowess but also adds a touch of innovation to a daily essential. Precision and Power: What sets Jagmeet's creation apart is its ability to display the actual time seamlessly upon power supply. The integration of microcontroller technology and servo motors exemplifies a harmonious blend of accuracy and creativity. Applauding Jagmeet Singh: Let's take a moment to applaud Jagmeet for his dedication and passion for pushing his boundaries. His digital clock project not only demonstrates his technical skills but also reflects the spirit of innovation that defines RTRA. Inspiring the Future: At RTRA, we believe in nurturing innovative thinkers who contribute to shaping the future. Jagmeet's project is a testament to the exciting possibilities that arise when students are empowered to explore their creativity in a supportive environment. #Innovation #EngineeringExcellence #RTRA #Robotics
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Catch #iCETS leader Prasad Joshi engaging with ACM President Yannis Ioannidis about the incredible energy at the ACM India PIC 2024. Dive deep with them as they discuss the exciting synergy between engineering and research. Read more about iCETS: infy.com/3zpEiQf #FutureProofingBusinesses Manjunatha Kukkuru ACM, Association for Computing Machinery
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Project Junior Research Fellow (Vehicular Technology) IIT ISM Dhanbad, Radio Frequency and Microwave frequency researcher, Filtenna, Full duplex antenna,3D printing material characterization
📢 Exciting News! My #WMAS2023 conference paper, " A Conformal, Planar Inverted F Antenna using Low-Cost Multilayer PET Sheet for Vehicular Application," has been published. I'm thrilled to share the key findings of this research, which dives into conformal PIFA antenna for vehicular application. I want to express my deep appreciation to my guide Dr. Ravi Kumar Gangwar (Associate Professor & HoD, Department of ECE, IIT (ISM) Dhanbad) their outstanding support and to my ME guide Dr. Garima Saini (Assistant Professor) and Dr. Balwinder Singh Dhaliwal (Associate Professor) at NITTTR Chandigarh for their guidance. This paper represents a significant step forward in our understanding of vehicular communication. I believe that its findings have the potential to advance the automobile system. If you're interested in reading the full paper, you can find it here doi: 10.1109/WAMS57261.2023.10242982. I would love to hear your thoughts and feedback! #Research #PublishedPaper #AcademicAchievement #WMAS 2023#Conformal Antenna
A Conformal, Planar Inverted F Antenna using Low-Cost Multilayer PET sheet for Vehicular Application
ieeexplore.ieee.org
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I just finished an amazing one-week crash course at NSUT in New Delhi called "Building with Tiny Tech: Designing Modern Chips (CMOS/FPGA 2024)". It was a deep dive into the world of how chips are built, from the super tiny (CMOS) to the super flexible (FPGA). The course covered a ton of cool stuff, like how to design entire systems on a single chip, how to make these tiny circuits use less power, and the whole process of bringing a custom chip idea to life. We also learned about designing high-performance analog circuits (the kind that deal with continuous signals) and how to mix those with digital circuits (the kind with 0s and 1s) to create even more powerful chips. We even got into the nitty-gritty of how these chips are physically laid out and built, which was mind-blowing! This course wasn't just about learning new things, it really opened my eyes to the incredible possibilities of the future with these tiny technologies. Huge thanks to the organizers, Dr. Urvashi Bansal and Dr. Shweta Gautam, and all the speakers for such an awesome and inspiring experience! Hashtags: #NSUT #VLSI #VLSIDesign #CMOS #FPGA #Semiconductor #DigitalDesign
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Excited to share a publication from ACM CHI Conference 2024: "Stick&Slip: Enabling Naturalistic Interaction with Touch Interfaces" by Alex Mazursky, Jacob Serfaty, and Pedro Lopes from the University of Chicago's Human Computer Integration Lab. Their innovative research introduces Stick&Slip, a novel approach that alters friction between the fingerpad and surfaces by depositing liquid droplets. This method allows users to experience surfaces as up to ±60% more slippery or sticky by modifying the finger’s coefficient of friction. Stick&Slip offers several advantages over traditional friction-feedback techniques, such as electroadhesion or vibration: 1. It can alter friction on a wide range of surfaces and geometries. 2. It scales to many objects without requiring instrumented target surfaces. 3. It can both increase and decrease friction via a single device. Seeed's XIAO microcontroller was utilized in this study, showcasing its versatility and precision in cutting-edge applications. 🔗 Read the full paper here: https://lnkd.in/gZTVbzEg Watch the video on YouTube: https://lnkd.in/gHKNeTh2 #CHI2024 #TouchInterface #HCI #Innovation #SeeedStudio #XIAO #research
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have a look at how University of Karlsruhe Institute of Technology is deploying xiRAID to create a fast cache to handle a 100PB of tape libraries. With just 10 NVMe in RAID6, KIT measured stable 50GB/s read and 25GB/s write, outperforming by a mile more complex and expensive alternatives. #xiRAID #Xinnor #RAID #NVMe #tapestorage #coldstorage #hotstorage #cache #performance #reliability #casestudy https://lnkd.in/dT_CCPbE
Karlsruhe Institute of Technology | Partners | Xinnor
xinnor.io
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Probabilistic Risk Assessment (PRA) of fail-operation/fault-tolerant systems | Tools & Technology for Nuclear Power Plants Safety | Safety assessment with MBSE (SysML 2.0) | Stochastic Verification | Model-checking
SAFEST, the most complete, effective, and scalable tool for dynamic fault trees (DFTs), can now be used to model and analyze reward event trees (RETs), event trees that include non-deterministic choices, and state rewards. DFTs and RETs can be combined by the embedding of DFTs into RETs that provide transition probabilities (of RETs). By analyzing RETs (integrated with DFTs), one can determine: Expected gains or losses, such as radioactive leakage, fatalities, etc., Limits on the frequencies and probability of the outcomes in event trees, and Wise choices to, for example, lessen the unfavorable effects/outcomes. A joint effort of my research group at Aachen, Twente University, and DGB Technologies. Check it out: www.safest.dgbtek.com Academic license for free for DFTs. More than a decade of research inside. Joost-Pieter Katoen Marielle Stoelinga Matthias Volk #reliability #formalverification #faults hashtag #dependability #robustness #modelling #gui #rewrite #drawing #simulation #eventtrees #Bowtie
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Very worthwhile insightful discussion for sustainability professionals: the application of the SSbD to the use case of flame retardants for electronis cmponents and EV parts. Some nice insights using the SSbD approach - and do feel free to ask Adrian about the practicalities of applying the SSbD in real life!
I am happy to be part of Electronics Goes Green 2024+ this June with a presentation on "Safe and Sustainable-by-Design of Phosphinate #FlameRetardants 🔥 - a case study for electronic components and electric vehicle parts". Learn more about the first fully hybrid EGG conference and register here: https://lnkd.in/ejBFKjsr #ElectronicsGoesGreen2024 #SSbD Fraunhofer IZM Co-authors 🙏 : Dr. Daniel Maga, Venkat A., Tomas Rydberg, Gerard Kwant
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Senior Software Engineer, Low Level & Embedded Systems Real Time programming, Micro-Electronics & FPGA, and IoT Engineer
Free Integrated Circuits : Abstract of my next presentation at #FSiC2024 conference (Free Silicon Conference 2024 - Paris - LIP6 - Sorbonne Université ) : " Unveiling the future of Free Integrated Circuits : Empowering Users with Home Integrity Check. "
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