Tessent Silicon Lifecycle Solutions

Its less than a week to go now till the start of the International Test Conference 2024 in San Diego. To kick off the week as always there is a whole program of exciting tutorials, I'm proud to be hosting one of those, focusing on the DFT trends and techniques for AI and large block based designs. Register here: https://lnkd.in/dcHxDVWJ

The quality of a test is best quantified by measuring the quality of ICs that pass the test after a device has been manufactured. However, there is significant value in analyzing test quality before high-volume production, to maximize test coverage while minimizing pattern count, something that digital ICs have done via fault modeling and simulation for many years. This webinar, which includes Tessent experts Steve Sunter and Vladimir Zickovic in the presenter line-up, is set to address key questions, including: - Why is test time per transistor much larger for analog than it is for digital circuits - Why is there so little automation for analog design-for-test (DFT) and test generation - How can a circuit's test coverage be measured objectively before manufacturing the circuit? The webinar, as well as defining some essential terms, such as defect, fault, defect universe, and defect coverage, will also describe several hypothetical industrial examples where P2427, the IEEE Draft Standard for Analog Defect Modeling and Coverage, can simplify, clarify, quantify and speed the delivery and description of AMS circuit and test quality. To learn more about 'How to create better analog IC tests' & to register, visit: https://sie.ag/71zEWK #AnalogIC #IEEE #DFT #DFTmarketleader #Tessent #designfortest #TessentStreamingScanNetwork #TessentSSN #SiemensEDA

Attending ISTFA 2024 this week? Be sure to join the Siemens EDA team in booth #401, to discover the full range of Yield learning solutions direct from Tessent experts. Also, while at ISTFA, make sure you don't miss these exciting presentations in the Technical Program: - Emerging FA Techniques and Concepts Solving Complex Electrical Fault Isolation Challenges with Innovative DFT Strategies - 1:20pm Tue, 9 Oct - Room 202 Google LLC: Lesly Endrinal, Rakesh Kinger, NOOR Jehan Saujauddin, Yuan Chung Ho, Wilson Pradeep, Shruti Mittal, Jyotika Suri and Atul Chittora. Siemens EDA: Dr. Mark Kassab and Peter Orlando - Improved Diagnosis Methods for the Era of Back Side Power 2pm, Wed, 30 Oct - Room 202 Presenter: Jayant D'Souza, Principal Technical Product Manager, Tessent. Learn more about the full ISTFA technical program and speaker line-up. https://sie.ag/5JswYA Alternatively you can learn about the full range of Tessent Yield Learning solutions now at. https://sie.ag/6MTSLS #HiResChain #YieldLearning #Scanchaindiagnosis #chiplets #DFT #Tessent #DFTMarketLeader #SiemensEDA #3DIC #semiconductors

It's a wrap at this week's RISC-V Summit North America after a very busy and knowledge sharing few days. It was a fantastic event for Siemens EDA and the Tessent Embedded Analytics team and we would like to say a big thank you to everybody that joined us in the booth and expressed interest in the Tessent RISC-V solutions that help organizations to manage the risk of adopting RISC-V architecture. We would also like to share a big congratulations to Iain Robertson, Senior Engineering Director - Hardware, Tessent, who received an award in recognition of specification ratification for Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V, at the show. We look forward to meeting you all again at future RISC-V Summits and would like to leave you with a quick recap of this year's event below. Learn more about Tessent RISC-V solutions today by visiting: https://sie.ag/EKne6 #RISCVSummit #RISCVeverywhere #TessentESDK #EmbeddedSDK #TessentEmbeddedAnalytics #SiemensEDA

A big thank you to all the delegates that visited the Siemens EDA booth at the IoT Security Foundation Conference 2024 that took place recently at the IET in London. Lee Harrison, Director Product Marketing and Rasadhi Attale, Senior Hardware Engineer, were on hand to introduce visitors to a range of comprehensive hardware security solutions for integrated circuit (IC) products that address protection and silicon lifecycle management and which span across test, functional operation and system-level security. Conference delegates were also able to enjoy a number of live expert Siemens EDA presentations, which included: - Hardware based security for advanced threat detection and mitigation - Presented by Rasadhi - For a few dollars more - Presented by Paul Hingley, in which he discussed the real cost of OT security A big thank-you also to our special guests at the conference, Yan-Tarō Clochard, CMO and Brice Gaignoux, Pre-sales Engineer, from Secure-IC. Check out the days proceedings in the photos below. You can also learn more about Tessent Safety and Security solutions today at: https://sie.ag/2oUEqH #AutomotiveCybersecurity #TessentSSN #TessentStreamingScanNetwork #DFTMarketLeader #Automotivesafety #semiconductors

Discover the benefits of using in-system deterministic test, and how using this new technology can become a central part of any SLM strategy in this latest Tessent webinar presented by Lee Harrison, Siemens EDA. Thanks to new industry innovations, it is now possible to apply manufacturing quality test patterns direct to a design, leveraging the benefits of deterministic test over transitional in-system test methods. Learn more and reserve your free webinar place today: https://sie.ag/2PxLu3 #DFTmarketleader #Tessent #designfortest #TessentStreamingScanNetwork #TessentSSN #SiemensEDA

Join Tessent at the International Test Conference (ITC) 2024 to discover market-leading design-for-test (DFT) solutions from Siemens EDA. We also invite you to join us for the exclusive Diamond event presentations where Ankur Gupta, Sr. Vice President and General Manager of Digital Design Creation Platform, Siemens EDA, hosts a special guest speaker line-up that includes Anurag Jindal, Head of DFX group with Ericsson, Vishal Agarwal, Sr. Director, H/W Engineering with NVIDIA and Dan Trock, Principal Engineer, Amazon Web Services (AWS), Annapurna Labs. Ankur will detail Siemens’ transformative technologies plus introduce an important new product for in-system test. Dan will explain how this new technology is already in silicon at Amazon AWS. Anurag will provide an insight into productivity gains using Tessent products at Ericsson, and Vishal will be sharing how Tessent Streaming Scan Network is being used in their challenging designs at NVIDIA. The Diamond event takes place on Tue, 5 Nov, from 10:45-11:45 in the main ballroom at the Hilton Bayfront San Diego (Sapphire CDGH). To learn more about the Diamond event, the conference program and to register, please visit. https://sie.ag/28j7bQ #ITCTestWeek #DFTmarketleader #Tessent #designfortest #TessentStreamingScanNetwork #TessentSSN #SiemensEDA

Attending the 50th International Symposium for Testing and Failure Analysis, #ISTFA, next week in San Diego? If so, we hope you will pop by booth #401, where experts from the Tessent team will be on hand to answer your questions and introduce you to the full range of Yield Learning solutions available from Siemens EDA, including the latest developments in Tessent YieldInsight. You can also enhance your learning experience with these technical presentations: - Solving complex electrical fault isolation challenges with innovative DFT strategies - 1.30pm Tue, 29 Oct - Improving diagnosis methods for the era of back side power - 2pm, Wed, 30 Oct | Presenter: Jayant D'Souza To learn more about ISTFA and to register to attend, just visit. https://sie.ag/f5YE To learn more about Tessent Yield Insight, visit. https://sie.ag/4a5Jna #HiResChain #YieldLearning #Scanchaindiagnosis #chiplets #DFT #Tessent #DFTMarketLeader #SiemensEDA #3DIC #semiconductors

There's still time to attend this week's IoT Security Foundation conference in London and to discover the range of Tessent safety & security solutions from Siemens EDA. You can meet the Tessent experts from Siemens EDA in booth #10 who will introduce you to a comprehensive hardware security solution for integrated circuit (IC) products, and solutions that address protection and silicon lifecycle management that span across test, functional operation and system-level security. There are also expert presentations from the team, including: - Hardware based security for advanced threat detection and mitigation - Presenter Rasadhi Attale, Senior Hardware Engineer. - For a few dollars more - Presenter Paul Hingley, discusses the real cost of OT security. To learn more and to register, just visit. https://sie.ag/2Pmho3 #AutomotiveCybersecurity #TessentSSN #TessentStreamingScanNetwork #DFTMarketLeader #Automotivesafety #semiconductors #industrialsecurity #iec62443 #NISV2 #CRC

In this podcast, Marc Hutner, explains how Yield Insights can be improved through AI, ML and other techniques that can result in millions of dollars of savings. Listen-in to the full podcast with SemiWiki.com now to learn more. https://lnkd.in/daNM69u9 #YieldLearning #yieldmanagement #TessentYieldInsight #DFTmarketleader #Tessent #semiconductor #SiemensEDA