Veriest

RISC-V is transforming the #semiconductor world, bringing flexibility, customizability, and a thriving ecosystem for chip design. But with these advantages come challenges in conformance, verification, and validation, as highlighted in Semiconductor Engineering's recent “Experts At The Table” discussion with industry leaders. [link below] Here are a few interesting insights: Frank Schirrmeister (Synopsys): “[With RISC-V], you can extend it and do your own thing, but then you’re out of luck because you have to verify all the changes you made.” John Min (Arteris): “As the CPU gets adopted more widely, we have third party software vendors writing software that assumes it is independent, and a hardware abstraction layer, assuming things will be compatible.” Neil Hand (Siemens): “There isn’t one solution for anything. You want to use a mix of #formal and #simulation to make sure your processor is correct. You want to be able to use the big boxes [#emulation] to make sure you’re running software on there. You want to be able to use virtual prototypes early to make the decision about whether to run this particular set of workloads on it, or to benchmark different processor vendors. It is all of these working together.” -- At Veriest, we’ve worked on numerous RISC-V projects, providing our clients with a full range of design and verification solutions. Whether it’s ISA compliance, custom instruction validation, or software compatibility testing, our experienced team brings expertise across the verification landscape, ensuring our clients’ RISC-V designs meet the highest standards. If you’re developing RISC-V-based solutions and want confidence that your designs are ready for market, let’s connect. Veriest can help you navigate the complexities of RISC-V verification and bring your vision to life.   #RISCv #semiconductors #Verification #Conformance #chipdesign #verification

Waiting for you at electronicaFair 2024! 👋 Let's meet in Munich to explore how Veriest's ASIC design and Embedded Software expertise can accelerate your semiconductor projects. Our team is ready to share insights and solutions that will bring your innovations to life. 📅 November 12-15, 2024 📍 Messe München, Germany Book your meeting: https://lnkd.in/d9-VS9vm #Electronica2024 #ASIC #Semiconductor #VerificationServices

We're excited to announce that Veriest will be attending #SEMICONEuropa 2024 in Munich Join us at this major trade fair for electronics development and production. Our team will be there to discuss how our semiconductor design and verification services can help accelerate your next project. 🤝 Ready to connect? Schedule a meeting with us: https://lnkd.in/d9-VS9vm 📅 November 12-15  📍 Munich, Germany #Semiconductors

Celebrating 7 incredible years of innovation and excellence at our Niš & Novi Sad sites!🎉 Our teams have consistently pushed the boundaries of semiconductor engineering. The talent, dedication, and technical expertise of our Serbian colleagues have been instrumental in delivering cutting-edge solutions to our global clients. Thank you to every team member who has contributed to this remarkable journey. Here's to many more years of growth, innovation, and success! 💫

May the festival of lights bring brightness, prosperity, and joy to all our clients, partners, and friends around the world. Happy Diwali from the Veriest family! 🕯️

Wishing all our clients, partners, and friends a spooktacular Halloween! From all of us at Veriest 🎃

Thank you Djordje for contributing to DVCON with your paper and presentation. Proud to have such talented engineers on our team! 💪🏻

Veriest made waves at DVCON EU as sponsor, exhibitor, and presenter! We stood out by delivering TWO papers - a rarity at this conference. Our exceptional presentations: 🌟 Milos Pericic: Constraint solver performance 🌟 Djordje Velickovic & Katarina Božinović: Functional verification Proud of our team's outstanding contributions! Curious about our innovative approaches? Subscribe to our newsletter for exclusive insights and future tech previews! https://lnkd.in/dnBeC4Y5

We're here and ready for you at DVCon Europe 2024! 🎉 Come meet our team at booth #04 to discuss innovative approaches in ASIC design and verification that can elevate your projects. See you at booth #04! #DVConEurope2024 #Verification #ASICDesign

Excited to share our upcoming presentation at DVCon Europe 2024 - Improved Performance of Constraint Solver by Milos Pericic A paper on improving the performance of constraint solvers in SystemVerilog. We explore practical techniques for enhancing randomization efficiency in complex verification environments. 📅 October 16th, 4:15 PM 📍 Forum 8 Can't wait to connect? Fill out our quick meeting request form, and we'll reach out to confirm a time that works for both of us.  👉 https://lnkd.in/deZUHVnd    #DVConEurope2024 #VerificationOptimization #SystemVerilog