Learn VLSI

Verilog Hardware Description Language (HDL) is a hardware description language used to model and design digital circuits. It is most commonly used in the design and verification of digital circuits. This presentation covers the following - Need for HDL Language - History - Where to start: VHDL, Verilog, SystemVerilog? - First Step for HDL - Verilog Fundamentals - Get familiar with keywords, syntax, operators, features, etc. - Testbench - Blocking, nonblocking, Operators, Flow controls, etc. - Timescales, inter and intra-assignment delay - Delta Delay - Steps for RTL Design - Simulation Tools - Learning Resources Udit Kumar, PhD #hdl #verilog #designverification

Low Power RTL Design refers to design practices that minimize power consumption in digital circuits. Optimizing for low power at the RTL level becomes crucial when designing digital systems, especially in applications with power constraints like battery-operated devices or IoT (Internet of Things) devices. Here are some key aspects and considerations in low-power RTL design: - Clock Gating - State machines encoding - Minimize transitions on the data path - Control over free-running counters - Gray encoding for memory address - Gray Coding for counters - Bus invert coding - Operand Isolation - Precomputation  - Shift Register Vs Circular Buffer - Sequential Gating Udit Kumar, PhD #lowpower #rtldesign #semiconductor

SoC clocking faces the following challenges: 1) The distribution of clocks has grown to be a more difficult issue for VLSI designs, requiring an increasing amount of wiring, power, and design time. 2) If the interconnect lengths in the clock delivery routes to two sequential registers vary significantly, clock skew may happen. 3) A clock jitter is the deviation of a clock edge from its ideal position in time. This lecture covers these challenges and solutions in detail. Credit: Mark McDermott, University of Texas at Austin Udit Kumar, PhD, Ganesh Prabhu #clocks #power #physicaldesign