VLSIVersity

We are looking for deep #UVM Testbench Architects & Implementation Experts for our next generation of IP products. Multiple positions now open for #Senior #DesignVerification Engineers for Cadence Design IP R&D Team, Bangalore. Experience: 7 to 12 Years (Multiple Senior Positions) Qualification: B.Tech/M.Tech (EE/EC/CS) Mandatory Skills: Strong SV/UVM/Testbench development skills with working knowledge of any generic protocols like PCIe/CXL/UCIe/USB/MIPI/Ethernet/DDR. Send your resume to: cdn_dip_hiring@cadence.com Add your years of experience in subject line. #SystemVerilog, #UVM, #PCIe, #CXL, #UCIe, #USB, #MIPI, #ethernet #bangalorehiring Navnit Kashyap, Vamsi Krishna Kilaru, Kiran Kumar Indrakanti, Saravana Balakrishnan, Rajesh Wasnik, Tejbal Prasad, Sakthivel Ramaiah, Sivaram Allamraju, Roopa Gupta, Supriya Dachapalli

Our team at Microsoft Azure Server development is currently seeking a strong DV candidate with 2-10 years of experience in SV, UVM, and testbench development. If you have a experience in DDR memory controller/PHY, then we like to hear from you. Please drop me a direct message. #MicrosoftAzure #ServerDevelopment #DV #SV #UVM #TestbenchDevelopment #DDRMemoryController #PHYExperience #JobOpening.

Hi Everyone, I'm happy to announce that my friends and I have created a blog which focuses on semiconductor practice questions, particularly the concepts of Verilog, SystemVerilog and UVM. Website address :  www.forkjoin.in The blog also exclusively hosts a number of theory and coding questions including interview questions targeted towards semiconductor engineers. Right now there's also a small case study on APB3 verification IP which can be used as a reference for how an industry testbench looks like. Feel free to reach out to me if you have any feedback, and otherwise please do share it with anyone who you think might find this helpful. Some Important Pages: SV Interview Questions -https://lnkd.in/gz_Rjjjb Randomization Questions - https://lnkd.in/gWuHAazX APB3 Verification IP - https://lnkd.in/gxj5YwXA #verification #vlsi #systemverilog #verilog #uvm #design #semiconductor #scenariobased Thanks to all the co authors J V M Durga Phaniteja Mannidi Padmakar Rao Mandiga Ram M Tarun Burra Shiva Reddy Varakantham Saurabh Gupta MD J TAZEER Vasudevarao Kalla

Cadence Hyderabad is currently seeking Verification Engineers with 4-10 years of experience. If you have a BE/BTech/ME/MTECH qualification and are proficient in DDR Protocol, USB3 protocol, and IP/Sub_System/SoC level verification, this opportunity might be for you! The responsibilities include developing test plans, creating verification environments, and driving verification closure through functional coverage. Key responsibilities: - Develop test plans, tests, and verification infrastructure for complex IP’s/sub-system/SOC’s. - Create verification environment using UVM methodology or equivalent. - Build reusable bus functional models, monitors, checkers, and scoreboards. - Drive verification closure through functional coverage. Desired skill sets: - BTech/ MTech in Engineering - 4-11 years of VLSI industry experience in Verification. - Proficiency in DDR Protocol (DDR5, LPDDR5/USB) and USB3 protocol.PCI - Expertise in IP/Sub_System/SoC level verification. - Strong in developing test bench/test cases using SV & UVM. - Experience in verification cycle for complex IP/SOC projects. - Familiarity with code coverage, functional coverage & assertions. - Knowledge of bus protocols (AXI/AHB/APB). If you are interested, please share your updated profile to dsupriya@cadence.com. Join us in shaping the future of technology!

#Qualcomm is hiring Wireless R&D RTL Design Verification Engineer. QCT's Bangalore Wireless R&D HW team is looking out for HW verification engineers to work on WRD IPs for Qualcomm’s best in class Mobile chipsets. Location : #Bangalore Years of experience : 1 to 4 years Roles and Responsibilities: You will be contributing to flagship modem IP verification covering 5G(NR), 4G (LTE) and 3G technologies. You will be part of team defining and developing next generation multi-mode 5G modems. ✏ Candidate must be able to take ownership of block/IP/core verification. Incumbent will be analyzing HW design spec and develop a verification test plan/strategy for it. ✏He / She will work with design team on RTL debug during Pre-silicon HW development phase. ✏Being adaptable and ability to work at various abstraction levels: Block/Core/IP/SS level. ✏Demonstrate strong coding skills in System Verilog and UVM. ✏Scripting languages like Perl/Python and development test automation framework for regression automation. ✏Deep understanding of Code/Functional coverage report, identify why coverage holes, ability to develop new and closing with design/systems team. ✏Performance verification for throughput/latency analysis would also be job requirement on selected blocks. ✏HW verification using Cadence and Synopsys simulator tools, SV/UVM based TB development, Regression analysis, bug-triage ✏Knowledge of Formal tools (Jasper) for Formal verification is a plus. ✏Conducting High-/Mid-/Low- level verification reviews, coverage closure and sign-off on block testing ✏Assisting SOC team with IP Integration testing at SOC level Deepak Garg | Nandhini Ramesh (She/Her) | Manju P Gowda | Rekha Palanisamy | Veena Jadav Interested engineers please upload the resume in the below link https://lnkd.in/gMWmY4Vt #verification #IP #subsystem #systemverilog #SV #Verilog #UVM #jasper #integration #perl #python #coreverification #formalverification

We are hiring #DesignVerification Engineer for Design IP R&D Team at Cadence, Bangalore. Experience: 4 to 12 Years (Multiple positions). Qualification: B.Tech/M.Tech (EE/EC/CS) Mandatory Skills: Strong SV/UVM/Testbench development skills with working knowledge of any generic protocols like PCIe/CXL/UCIe/USB/MIPI/Ethernet/DDR. Send your resume to: cdn_dip_hiring@cadence.com Add your years of experience in subject line. #SystemVerilog, #UVM, #PCIe, #CXL, #UCIe, #USB, #MIPI, #ethernet #bangalorehiring Navnit Kashyap, Vamsi Krishna Kilaru, Kiran Kumar Indrakanti, Saravana Balakrishnan, Rajesh Wasnik, Tejbal Prasad, Sakthivel Ramaiah, Sivaram Allamraju, Roopa Gupta, Supriya Dachapalli

Synopsys is seeking ASIC/IP Verification Engineers in Bangalore and Noida with expertise in UVM and OVM methodologies. Ideal candidates will hold a bachelor’s or master’s degree in engineering and have 4 to 10 years of relevant experience. This role is part of the VIP group, dedicated to Verification IPs. If you are ready to tackle new challenges and join an innovative team, send your resume to taufiq@synopsys.com. Take advantage of this opportunity to work alongside an energetic team.

We are hiring #FormalVerification Engineer for Interface Controller IP R&D Team at Cadence, Bangalore. Experience: 4 - 6 Years and 7 - 9 Years. Skills Expected: Strong Verilog, SVA and Formal environment development skills with working knowledge of any generic protocols like AMBA/USB/PCIe/CXL/UCIe. Having experience in Formal Verification is mandatory. Should have signed off multiple RTL blocks using Formal Verification. Having experience in complexity handling and deep bug hunting techniques preferable. Need a candidate who is inclined to take technical leadership roles. Send your resume through Linkedin or email to cdn_dip_hiring@cadence.com. Please mention "Formal" in the subject line. #SystemVerilogAssertion #Jasper #VCFormal #QuestaFormal