DataAnalytics.Report’s Post

Synopsys Inc raised its annual revenue and profit forecast on Wednesday in anticipation of robust demand for its software to design advanced chips driving artificial intelligence applications. The AI-boom has spurred investments in custom design of chips as tech firms are racing to dominate the lucrative technology with new innovations, triggering demand for companies such as Synopsys. Chief Executive Sassine Ghazi said demand for the company's core products remained strong, with revenue from them expected to grow 15% this year as customers design their own chips for AI and other purposes. The company raised its annual revenue forecast in a range of $6.09 billion to $6.15 billion, compared with its prior expectations of $6.06 billion to $6.12 billion. With Stephen Nellis #Synopsys #Semiconductor #ArtificialIntelligence https://lnkd.in/g2Yq73mH

Cadence Design Systems's evolution mirrors the ever-changing #semiconductor industry. As customized chips become increasingly common, Cadence is adapting its expertise to meet the growing demand for tailored solutions. This demand stems from the convergence of various factors, such as applications, software stack, user experience, system, board, package, and #chip, which is compressing schedules and introducing unprecedented complexity. By embracing #AI, advanced #simulation techniques, and #cloudcomputing, Cadence is positioned to transform the semiconductor industry, ushering in a new era of efficiency, #innovation, and unparalleled technological advancement. Learn more:

A good read about few products at #synopsys

Synopsys Unveils World’s Fastest UCIe-Based Multi-Die Designs with New 40Gbps IP >Exciting news from Synopsys! They have introduced the industry’s first complete UCIe IP solution capable of operating at an impressive 40Gbps per pin. This groundbreaking innovation is set to revolutionize multi-die system-on-chip (SoC) designs, addressing the growing data requirements in high-performance computing environments. Key Highlights: Unmatched Speed: The new IP solution is UCIe compliant at 32Gbps per pin and can achieve speeds up to 40Gbps per pin in specific use cases. Comprehensive Solution: Synopsys’ 40G UCIe IP includes the controller, PHY, and verification IP, ensuring seamless integration and fast connectivity between heterogeneous and homogeneous dies. Enhanced Performance: By increasing the data transfer rate, Synopsys ensures that multi-die SoCs can efficiently handle the demands of AI data centers and other high-performance applications. Reliability: Integrated signal integrity monitors and testability features improve multi-die package reliability and enable in-field monitoring throughout the silicon lifecycle. This innovation boosts performance and maintains energy efficiency and a compact silicon footprint, making it a game-changer for the semiconductor industry. #Semiconductors #TechInnovation #UCIe #HighPerformanceComputing #Synopsys #TechTrends #AI #LinkedIn 😊 Ref: 1: SemiWiki Could you follow along for timely updates on the latest in the semiconductor industry and technologies?

#AI, Synopsys to buy Ansys in a push into AI, chip design megatrends; Cash-and-stock deal valued at $35 billion Synopsys Inc. confirmed an agreement to buy design-software company Ansys Inc. in a cash-and-stock deal valued at $35 billion, as the companies look to ride the AI and semiconductor-design "megatrends." "We know Ansys very, very well from a long-standing relationship dating back to 2017," Synopsys Chief Financial Officer Shelagh Glaser said in an interview. "Our products and services are extremely collaborative from the mechanical and industrial expertise of Ansys, as well as our digital expertise." Synopsys Chief Executive Sassine Ghazi said that with the "megatrends of AI, silicon proliferation and software-defined systems" requiring more computing performance, merging the companies will provide "holistic, powerful and seamlessly integrated silicon to systems approach to innovation" to maximize research and development. #RB, #AI https://lnkd.in/eGW3MxMx

[AI Infrastructure] UCIe Chiplet PHY Designer – As AI workloads evolve and change, chiplet based system architectures can be used to scale up quickly to keep pace with the growing compute needs. This demo will showcase a new PHY designer for chiplets that allows the modeling, simulation, and analysis of the high-speed channel between two D2D PHY interfaces. Enabling PCIe 7.0 Technology – PCIe architecture provides a robust high-bandwidth interconnect solution for attaching compute chips and network devices used in AI / ML applications. It also has the added benefit of a mature ecosystem that has been built up to include a compliance testing framework to ensure interoperability between different vendors. This will demonstrate Keysight’s solutions that can be used to enable the testing of PCI Express 7.0 transmitter and receiver technologies. PCIe 6.0 and CXL 2.0 Solutions – The rapid deployment of AI accelerators for use in compute arrays has driven the demand for higher speed PCIe chip-to-chip interfaces. Keysight’s PCIe 6.0 Analyzer and PCIe 6.0 Exerciser solutions will be used to show how live PCIe 6.0 protocol traffic can be generated and analyzed using advanced triggers and filters while emulating both root complex and endpoint scenarios. 1.6T 212G PHY Transmitter/Receiver Testing – In order to process the large datasets associated with AI and large language models, bandwidth improvements are needed in both the compute-oriented interfaces as well as those used to enable higher speed data networks. Keysight will demonstrate the testing and validation of next-gen SerDes designs running at 212 Gbps per lane which are used to enable high-performance computing to unleash the potential of AI.

Check out this good read article “Data Coherence Across Silos and Hierarchy of Semiconductor Engineering 🔔 Data abstractions—essential for the “shift left,” “extend right,” and “stretch sideways” strategies—are like puzzle pieces scattered across silos.  Strategy: Coherent data flow bridges the gaps. Think of it as a digital handshake across hierarchies. Semiconductor design isn’t just about transistors—it’s about data coherence. So, grab your pocket protector, sync your spreadsheets, and let’s build chips that sing in harmony. 👉 Follow our page Start With WCPGW for more chip-tastic content! 🤖🔌 #DataSecurity #Encryption #CyberSecurity #TechTips #hardwaresecurity #dataprotection #security #StaySafeOnline #startwithwcpgw #wcpgw #SemiconductorDesign #DataCoherence #TechInsights

https://lnkd.in/dKiAuDWk I saw today in a post by Kurt Keutzer that Prof. Sharad Malik won the most influential paper award on Chaff by DAC. I have to say in one sentence: CONGRATULATIONS ON THIS WELL DESERVED AWARD FOR YOUR CREATION OF TECHNOLOGIES THAT CHANGED HOW THE INDUSTRY USES FORMAL VERIFICATION TODAY. I decided to write this "Tales from EDA" in honor of Prof. Sharad Malik. I have to share some points in my history where I had the honor to work with Sharad, and where our paths have crossed many times. As I have said to Aart de Geus while I was working at Synopsys in a 1-1 once, the cooperation between Sharad and I had deeply impacted Verplex Systems and Jasper Design Automation, both of which acquired by Cadence Design Systems. At Verplex in 2000-2001, we were competing against Formality, and because we were a small company, the scenario was not good, because Synopsys was steadly gaining steam on our business, and it would be a matter of time until we would not be able to close deals any longer. At that time, I was working under KC Chen (CTO for Verplex Systems), and he asked me to scout new technologies to help Verplex. When I saw Zchaff paper, I contacted Prof. Sharad Malik, and I was able to quickly evaluate the technology, seeing that it would put us ahead of competition for several years. I immediately recommended that we should switch from our SAT solver (we used at that time GRASP) to Zchaff, and I personally negotiated to bring Prof. Sharad Malik to the Technical Advisory Board of Verplex. That decision gave us an edge against the competition that eventually led Verplex Systems to be acquired by Cadence Design Systems. A few years later, when I became a VP at Jasper Design Automation (and later on SVP of Engineering), I personally negotiated to bring Prof. Malik again to the Technical Advisory Board of Jasper, and we had fruitful colaborations in my 10-year run at Jasper, until it was acquired by Cadence Design Systems. Finally, in 2017, I was the VP of NVXL, I said any new company that I work will have Sharad in the TAB, and I again brought Prof. Sharad Malik to assist us in Deep Learning inference acceleration, and although the NVXL was not successful, NVXL set the initial road to AI acceleration engines, as one of the first companies to tap the market in that area. I have to say that I am honored to have worked with Prof. Sharad Malik in these three times, and this award is a well deserved one, as Prof. Sharad Malik influenced the success of Verplex Systems and Jasper Design Automation, and on how the whole industry today sees formal verification.

Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design. Synopsys, Inc. (Nasdaq: SNPS) today announced its continued, close collaboration with TSMC to deliver advanced EDA and IP solutions on TSMC’s most advanced process and 3DFabric technologies to accelerate innovation for AI and multi-die designs. The relentless computational demands in AI applications require semiconductor technologies to keep pace. From an industry leading AI-driven EDA suite, powered by Synopsys.ai™ for enhanced productivity and silicon results to complete solutions that facilitate the migration to 2.5/3D multi-die architectures, Synopsys and TSMC have worked closely for decades to pave the path for the future of billion to trillion-transistor AI chip designs. https://lnkd.in/gXbeJ3gB Synopsys Inc #Synopsys #TSMC #TrillionTransistorChips #AIChipDesign #CoWoS #SiliconProvenIP #MultiDieArchitecture #EDA #3DFabric #AIDrivenEDA #BacksidePowerDelivery #AdvancedProcessNodes #ChipDesignInnovation #MultiPhysicsFlow #HBM4IP 

#AI is transforming #semiconductor design by automating tedious tasks, enhancing creativity, and enabling innovative #chip architectures, all while addressing the growing #workforce gap in the industry. See how in this article from Synopsys Inc. #artificialintelligence