Radley James’ Post

Oxide is hiring software engineers! https://lnkd.in/g6v6yjmj This has been such a cool place to work. We aren't kidding about being able to work at almost every level of our software stack: in my time here I've gotten to - dig into AMD's architecture manuals to decide what processor features to expose to our guests - take our first steps toward emulating PCIe support in our virtual machine monitor (this was my starter project!) - build (from scratch) an integration test framework for that VMM - read up on our OS internals to understand how their CPU and memory governance features work and how to use them - reason through some of the gnarly distributed systems problems in our control plane (and learn some TLA+ in the process!) - build out the VMM and control plane interactions we needed to migrate VMs between our compute sleds - say "when I got up today I didn't think I'd be reading the ACPI spec by lunchtime" We have a ton of fascinating OS, virtualization, and systems programming work on offer--take a look!

🚀 First Verification Project Complete! 🚀 I'm excited to share the successful completion of my first verification project: FIFO Verification using SystemVerilog and Assertions! This project involved verifying a synchronous FIFO (First In, First Out) design, which ensures data is processed in the same order it was received—critical for systems involving clock domain transfers and data communication. The verification flow included writing an extensive testbench, using assertions to catch edge cases, and implementing a coverage-driven verification plan to ensure thorough testing. 🎯 Key Highlights: Used SystemVerilog Assertions (SVA) to detect design violations in real-time. Achieved significant functional coverage using a custom coverage package. Found and fixed several bugs, such as underflow/overflow handling and reset logic errors. Debugged FIFO pointers and data count conditions to ensure proper flow management. This project was done under the insightful guidance of Kareem Waseem Wassem, who helped refine my verification skills and ensured the project met industry standards. Looking forward to more challenging verification projects in the future! #SystemVerilog #Assertions #FIFO #Verification #DigitalDesign #FPGA #RTL #Engineering

🚀 Excited to dive into the world of RISC-V microarchitecture? Check out this comprehensive course on RISC-V Microarchitecture, RTL Design, and Verification! 🎓 What You'll Learn: -> RISC-V basics, microarchitectures, and performance analysis. -> In-depth understanding of single and multicycle processors, including pipelined processors. -> Detailed walkthroughs of RTL (Verilog) design and testbench for single-cycle processors. -> Advanced topics like deep pipelines, branch prediction, superscalar, and out-of-order processors. -> Multithreading and multi-core concepts, with practical insights into the ibex RISC-V core. 🔗 Book now at vlsideepdive and take a giant leap in your career! 📞Contact to book - https://lnkd.in/gVpirNhG #RISCV #Microarchitecture #RTLDesign #Verification #OnlineCourse #TechCareer #VLSDiveDeep

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Layered architecture is a design pattern that divides the verification environment into multiple layers, each with a specific function and responsibility. This helps to create a modular, reusable and scalable verification code that can be easily maintained and debugged. Some of the common layers in a verification environment are: - Test layer: This layer contains the test scenarios and sequences that generate stimulus for the design under test (DUT). - Environment layer: This layer contains the components that interact with the DUT, such as drivers, monitors, checkers, scoreboards and coverage collectors. - Configuration layer: This layer contains the parameters and settings that control the behavior and functionality of the environment components. - Utility layer: This layer contains the common functions and methods that are used by the other layers, such as logging, reporting, randomization and synchronization. By using layered architecture, verification engineers can achieve better code quality, readability and reusability, as well as faster verification cycles and higher coverage. Crash course in verification! Fast-track your career with practical SystemVerilog training: https://lnkd.in/gTWbpPGx #careergoals #systemverilog #verification

Hi LinkedIn Tribe😎, My team in#TESSOLVE#bangalore/Hyderbad looking for candidates with an experience of 2.5-12 yrs. 🚀#Physical Design (PD) 🚀#STA Engineer 🚀 #Physical Verification(PV) 🕑 Notice period: Immediate joiner Candidates share your resume to soundar.selvanagarajan@tessolve.com ✅ 🏅 How to Fix a Setup Violation 🏅 ⛹♀️ Multi-Cycle Path (MCP) 🚰This method has some similarities to pipelining. Similarly, we will let the combinational path finish in multiple cycles. 🚰The difference is we won’t add pipeline registers. Instead, we will capture the data at another capture clock edge This can be done in 2 ways: 🚰Use a control circuit to mask the 1st capture edge and allow another one. 🚰 Use a divided clock for the capture FF as shown in the diagram below

Join us Work with cutting-edge technologies. Utilize your problem-solving ability in day-to-day software development. DM for a referral with the serial number. #ProblemSolving #Algorithm #DS #JOBS #Semiconductor #KLA #development #simulation #opticalPhysics #Connection

I am hiring Senior Engineers for my team: Design (RTL) : Candidates with exposure to micro-arch development, Spyglass, Synthesis, Timing Analysis, Processor domain knowledge are preferred. Verification: Candidates with exposure to SV, UVM, Power-Aware Sim, GLS, Processor domain knowledge are preferred. Experience Level: 5-10 yrs Interested candidates can reachout to me over DM.. #verification #processor #systemverilog #uvm #rtl #synthesis #design #architecture

4 of 35 #job #openings on 5/8 ✴️ NAND #product #development ✴️ Micron Technology #checkitout, #share and #follow! #opportunity #usajobs #usa #hiring #singaporejobs #hiringnow #open #jobsearch #reshare #engineeringjobs #engineering #givingback #spreadtheword #connectandgrow #repost

Shout out to all #physicaldesigners and #designverificationengineers with experience range between 3 to 9 years willing to work on a world class product. You may inbox me your resumes here at LinkedIn. For any queries please feel free to write me here in the comment box. #physicaldesigners #PDEngineer #STA #PnR #clocktreeanalysis #PlacementRoute #Verificationengineer #Verilog #VHDL #Systemverilog #designverification #hiring