Overcoming Forksheet Manufacturing Challenges: Precision Etching Monitoring with the AKONIS SIMS Tool
Imec is the developer of fully functional integrated forksheet field-effect transistors (FETs) and views it as the most promising architecture for advancing beyond the GAA nanosheet generation for scaling and performance improvements past the 2nm technology node.
Vertically-stacked nanosheet transistors are beginning to replace FinFET transistors, which struggle with performance at smaller dimensions. However, the close proximity of n and p devices in nanosheets presents challenges for further reducing cell height.
Imec's forksheet device is an evolution of the GAA nanosheet. It incorporates a tri-gate forked structure with a dielectric wall between the p- and nMOS devices, enabling tighter n-to-p spacing.
According to imec, TCAD simulations confirm the design enhances area and performance scalability by reducing Miller capacitance. The forksheet device offers track height scaling from 5T to 4.3T and increased drive current potential. Electrical characterization results indicate that the forksheet is the leading architecture for extending logic and SRAM scaling beyond 2nm in a non-disruptive manner.
Dr. Alexis Franquet, R&D Team Leader and Senior Researcher in the Compositional Analysis team focusing on Magnetic Sector, Time Of Flight, and Orbitrap-SIMS, highlights the necessity of evolving transistor technology from FinFETs to nanosheet (NS) or forksheet (FS).
"For 20 years, processors have featured vertical channel transistors known as FinFETs, which look like fins because they are tall relative to their width. As compared to planar transistors, the fin provides better control of the channel formed within the fin. As a result, FinFETs have been able to better deal with current leakage, which at the 3nm process node and beyond, may no longer be the case, so FinFET transistors will gradually give way to nanosheet (NS) or forksheet (FS) transistors, developed by imec, in high-volume manufacturing because these types of Gate-All-Around (GAA) devices offer better scaling and performance per unit area," Dr. Franquet stated.
The Manufacturing Challenge — and Solution
From a manufacturing perspective, forksheet devices are extremely complex to process. The challenges are detailed in the abstract, Etching Monitoring of Advanced Forksheet Devices Using the AKONIS SIMS Tool(1). A summary of the abstract follows.
The manufacturing process involves several types of dielectrics used in advanced CMOS. It necessitates multiple etching steps, requiring analytical tools with extreme sensitivity. The etching processes must be executed without accidentally damaging the walls, a critical requirement for manufacturers who need precise and sensitive analytical techniques.
Enter CAMECA's AKONIS fully automated SIMS for high-volume semiconductor manufacturing. This state-of-the-art analytical tool features a novel ion source integrated into a redesigned ultra-low-energy primary column with seamlessly automated beam optics. In fully automated analysis mode, it achieves relative standard deviations (RSD) of less than 1% for dose measurements across a broad array of applications.
AKONIS effectively measures 80µm x 80µm OCD pads of forksheet devices with exceptional analytical performance — outperforming other SIMS instruments.
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AKONIS monitors Ge concentration variations during etching and estimates the percentage of Ge remaining. Its superior single detection system and unique high extraction field technology provide a very high dynamic range with unparalleled depth, resolution, and sensitivity.
The CAMECA applications lab analyzed three samples at three different etching rates on the AKONIS. Figure 2 displays TEM images of the three samples with SiGe in unetched, half-etched, and fully etched states.
The main challenge is achieving optimal depth resolution while maintaining sufficient signal and statistics to characterize the fully etched sample. Figure 3 shows an overlay of the three profiles acquired on 80µm x 80µm OCD pads with SiGe forksheet devices in unetched, half-etched, and fully etched states.
Due to AKONIS's exceptional performance, the profiles clearly distinguish the different SiGe stacks, even for the fully etched sample.
The percentage of Ge remaining was estimated by calculating the integral of the Ge signal, using the unetched sample as a reference, with its Ge signal integral assumed to be 100% Ge. (Table 1).
The AKONIS SIMS tool outperforms other analytical systems in the etching monitoring of advanced forksheet structures, with excellent depth resolution while maintaining high sensitivity.
With superior analytical capabilities, full automation, and ease of use, the AKONIS SIMS tool is uniquely positioned to meet the requirements of current and future logic devices.
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Notes:
1: Robbes, A.-S., Dulac, O., Soulard, K., Adier, M., Choi, S., Jacobson, D., Merkulov, A., Tilmann, R., van der Heide, P. A. W., & Franquet, A. (2024). Etching monitoring of advanced forksheet devices using AKONIS SIMS tool. CAMECA, IMEC. Presented at the 2024 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics (FCMN). https://bit.ly/4aVn2zB