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ORCID28th FPL 2018: Dublin, Ireland
- 28th International Conference on Field Programmable Logic and Applications, FPL 2018, Dublin, Ireland, August 27-31, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-8517-4
Session M1A: Design Tools
- Xuegong Zhou, Lingli Wang, Peiyi Zhao, Alan Mishchenko:
Fast Adjustable NPN Classification using Generalized Symmetries. 1-7 - Henri Fraisse, Dinesh Gaitonde:
A SAT-based Timing Driven Place and Route Flow for Critical Soft IP. 8-15 - Chirag Ravishankar, Dinesh Gaitonde, Trevor Bauer:
Placement Strategies for 2.5D FPGA Fabric Architectures. 16-20 - Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic
, Philip Brisk:
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model. 21-25 - Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt:
Hierarchical Force-Based Block Spreading for Analytical FPGA Placement. 26-29 - Alex Rodionov, Jonathan Rose:
Automatic Topology Optimization for FPGA Interconnect Synthesis. 30-34
Session M1B: ML Architectures
- Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz:
Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs. 35-42 - Bogdan Pasca, Martin Langhammer:
Activation Function Architectures for FPGAs. 43-50 - Peng Guo, Hong Ma, Ruizhi Chen, Pin Li, Shaolin Xie, Donglin Wang:
FBNA: A Fully Binarized Neural Network Accelerator. 51-54 - Mihailo Isakov, Alan Ehret, Michel A. Kinsy:
ClosNets: Batchless DNN Training with On-Chip a Priori Sparse Neural Topologies. 55-59 - Cheng Luo, Yuhua Wang, Wei Cao, Philip H. W. Leong, Lingli Wang:
RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks. 60-63 - Di Wu, Jin Chen, Wei Cao, Lingli Wang:
A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration Architecture. 64-67
Session M2A: Runtime Methods
- Ibrahim Ahmed, Shuze Zhao, James Meijers, Olivier Trescases, Vaughn Betz:
Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs. 68-75 - Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, Krste Asanovic:
DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles. 76-80 - Robert Hale, Brad L. Hutchings:
Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs. 81-84 - Behzad Salami, Osman S. Unsal, Adrián Cristal:
Fault Characterization Through FPGA Undervolting. 85-88
Session M2B: Machine Learning Architectures
- Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott:
FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs. 89-96 - Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong, David Boland:
Customizing Low-Precision Deep Neural Networks for FPGAs. 97-100 - Yongming Shen, Tianchu Ji, Michael Ferdman, Peter A. Milder:
Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces. 101-105 - Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. 106-110
Session M3A: Cloud/Databases
- Anuj Vaishnav, Khoa Dang Pham, Dirk Koch, James Garside:
Resource Elastic Virtualization for FPGAs Using OpenCL. 111-118 - Zsolt István, Gustavo Alonso, Ankit Singla:
Providing Multi-tenant Services with FPGAs: Case Study on a Key-Value Store. 119-124 - Philippos Papaphilippou, Wayne Luk:
Accelerating Database Systems Using FPGAs: A Survey. 125-130 - Anuj Vaishnav, Khoa Dang Pham, Dirk Koch:
A Survey on FPGA Virtualization. 131-138
Session M3B: Machine Learning Frameworks
- Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha:
A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. 139-146 - Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk, Xinyu Niu:
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA. 147-154 - Alexandros Kouris, Stylianos I. Venieris, Christos-Savvas Bouganis:
Cascade^CNN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks. 155-162 - Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin, Deming Chen:
Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA. 163-169
Session T1A: Networking and Connectivity
- Athanasios Stratikopoulos, Christos Kotselidis, John Goodacre, Mikel Luján:
FastPath: Towards Wire-Speed NVMe SSDs. 170-177 - Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf:
FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet. 178-185 - Shanker Shreejith, Ryan A. Cooke, Suhaib A. Fahmy:
A Smart Network Interface Approach for Distributed Applications on Xilinx Zynq SoCs. 186-190 - Qingqing Xiong, Anthony Skjellum, Martin C. Herbordt:
Accelerating MPI Message Matching through FPGA Offload. 191-195
Session T1B: High Performance Applications
- Tyrone Sherwin, Kevin I-Kai Wang, Prabu Thiagaraj, Oliver Sinnen:
Median Filtering with Very Large Windows: SKA Algorithms for FPGAs. 196-201 - Nikolaos Alachiotis, Charalampos Vatsolakis, Grigorios Chrysos, Dionisios N. Pnevmatikatos:
Accelerated Inference of Positive Selection on Whole Genomes. 202-209 - Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu:
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing. 210-214 - Nina Engelhardt, C.-H. Dominic Hung, Hayden Kwok-Hay So:
Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems. 215-218 - Jiayi Sheng, Chen Yang, Martin C. Herbordt:
High Performance Communication on Reconfigurable Clusters. 219-223
Session T2A: Dynamic Reconfiguration
- Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, Nandeesha Veeranna:
CIDPro: Custom Instructions for Dynamic Program Diversification. 224-229 - Marie Nguyen, James C. Hoe:
Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration. 230-234 - Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, André DeHon:
Case for Fast FPGA Compilation Using Partial Reconfiguration. 235-238 - Takuya Kojima, Hideharu Amano:
A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures. 239-242
Session T2B: Architecture
- Ameer M. S. Abdelhadi, Guy G. F. Lemieux, Lesley Shannon:
Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories. 243-250 - Lake Bu, Michel A. Kinsy:
Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions. 251-255 - Ankit Wagle, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area. 256-259 - Dustin Richmond, Michael Barrow, Ryan Kastner:
Everyone's a Critic: A Tool for Exploring RISC-V Projects. 260-264
Session T3A: High Level Synthesis
- Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch:
ILP-Based Modulo Scheduling and Binding for Register Minimization. 265-271 - Charles Lo, Paul Chow:
Multi-fidelity Optimization for High-Level Synthesis Directives. 272-279 - Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Oliver Sinnen, Andreas Koch:
Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis. 280-286
Session T3B: Machine Learning
- Hongxiang Fan, Ho-Cheung Ng, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation. 287-294 - Muhsen Owaida, Gustavo Alonso:
Application Partitioning on FPGA Clusters: Inference over Decision Tree Ensembles. 295-300 - Jia Liu, Qiang Liu:
Resource Reduction of BFGS Quasi-Newton Implementation on FPGA Using Fixed-Point Matrix Updating. 301-306
Session W1A: Arithmetic
- Yaman Umuroglu, Lahiru Rasnayake, Magnus Själander:
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing. 307-314 - François Serre, Markus Püschel:
A DSL-Based FFT Hardware Generator in Scala. 315-322 - Debdeep Mukhopadhyay, Debapriya Basu Roy:
Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECC Application in GF(p). 323-326 - Luís Fiolhais, Horácio C. Neto:
An Efficient Exact Fused Dot Product Processor in FPGA. 327-330 - Ahmet Can Mert, Hasan Azgin, Ercan Kalali, Ilker Hamzaoglu:
Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA. 331-334
Session W1B: Computer Vision and Graphics
- Michael Barrow, Steven M. Burns, Ryan Kastner:
A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation. 335-342 - Georgios Chatzianastasiou, George A. Constantinides:
An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics. 343-350 - Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones:
A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. 351-354 - Tobias Alonso, Mario Ruiz, Angel Lopez Garcia-Arias, Gustavo Sutter, Jorge E. López de Vergara:
Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip. 355-359
Session W2A: Design Approaches
- Mustafa Abbas, Vaughn Betz:
Latency Insensitive Design Styles for FPGAs. 360-367 - Zhenhao He, David Sidler, Zsolt István, Gustavo Alonso:
A Flexible K-Means Operator for Hybrid Databases. 368-371 - Jonathan Déchelotte, Russell Tessier, Dominique Dallet, Jérémie Crenne:
Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping. 372-375 - Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, José L. Núñez-Yáñez:
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. 376-380
Session W2B: Machine Learning - Tools
- Stylianos I. Venieris, Christos-Savvas Bouganis:
f-CNNx: A Toolflow for Mapping Multiple Convolutional Neural Networks on FPGAs. 381-388 - Andreea-Ingrid Cross, Liucheng Guo, Wayne Luk, Mark Salmon:
CRRS: Custom Regression and Regularisation Solver for Large-Scale Linear Systems. 389-393 - Tong Geng, Tianqi Wang, Ahmed Sanaullah, Chen Yang, Rushi Patel, Martin C. Herbordt:
A Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Work and Weight Load Balancing. 394-398 - Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. 399-402
Session W3A: Overlays/CGRAs
- Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton:
An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. 403-410 - Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu:
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. 411-418 - Thiem Van Chu, Kenji Kise:
An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs. 419-426
Session W3B: Machine Learning and Model Checking
- Dani Maarouf, Abeer Alhyari, Ziad Abuowaimer, Timothy Martin, Andrew David Gunter, Gary Gréwal, Shawki Areibi, Anthony Vannelli:
Machine-Learning Based Congestion Estimation for Modern FPGAs. 427-434 - Shenghsun Cho, Michael Ferdman, Peter A. Milder:
FPGASwarm: High Throughput Model Checking on FPGAs. 435-442
PhD Forum
- Yao Liu, Ray C. C. Cheung, Hei Wong:
Lightweight Secure Processor Prototype on FPGA. 443-444 - Jan Kühn, Yiannos Manoli:
An Application-Specific Field-Programmable Tree Ensemble Architecture. 445-446 - Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis:
Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems. 447-448 - Habib ul Hasan Khan, Diana Göhringer:
Cycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs Using Artificial Intelligence. 449-450
Demo Night Papers
- Behzad Salami, Osman S. Ünsal, Adrián Cristal:
A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs. 451-452 - Declan Byrne, Ronan Farrell, Sidath Madhuwantha, Miriam Leeser, John Dooley:
Digital Pre-distortion Implemented Using FPGA. 453-454 - Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek:
Accelerated Wire-Speed Packet Capture at 200 Gbps. 455-456 - Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato:
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). 457-458 - Fearghal Morgan, Declan O'Loughlin, Jeremy Audiger, Yohan Boyer, Frank Callaly:
viciLogic2.0 Online Learning and Prototyping Using PYNQ. 459-460 - Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. 461-462 - Simone Casale Brunet, Thierry Schüpbach, Nicolas Guex, Christian Iseli, Alan J. Bridge, Dmitry Kuznetsov, Christian J. A. Sigrist, Phillippe Lemercier, Ioannis Xenarios, Endri Bezati:
Towards in the Field Fast Pathogens Detection Using FPGAs. 463-464 - Yi Shan:
ADAS and Video Surveillance Analytics System Using Deep Learning Algorithms on FPGA. 465-466
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