Unified Patents’ Post

#question_of_the_day #constraints #systemverilog #uvm Two dimensional Array: How to write constraint to generate unique elements in each location? https://lnkd.in/gGcgGhPe

Matt Oztalay's talks on optimizing UE5 are amazingly in-depth and you should NOT skip on these, there's knowledge here that hasn't been shared anywhere else! We just uploaded Part 1 on Nanite and Lumen, right here: https://lnkd.in/dYHf8DYx Part 2 focuses on VSMs, TSR, and World Partition performance, another treasure trove of advanced knowledge. Click it! https://lnkd.in/dnqhiBqU

behind the SystemVerilog official standard, there’s the de-facto standard: features supported by practically any vendor, that are still not part of the standard (Perhaps simply because no one had the time to rewrite the section) A good example is calling $assertoff from a class using a string. It makes perfect sense, but if you are as Catholic as the standard, it's a no. So, you might be wondering if it's safe to use in your code. That’s where edaplayground becomes really handy. Head over there and run your "non-standard” code on all simulators. If they all agree, you don't need to wait for 2027 LRM. in case you wonder, assertoff(path_string) is all good: https://lnkd.in/dGJAA5qt

I've developed a simple tool that facilitates the use of the Mixtral8x7B-Instruct Language Model on consumer-grade GPUs (it requires a minimum of 8GB of VRAM). This tool is built upon the excellent work of Artyom Eliseev and Denis Mazur, who developed a method to reduce the VRAM require for loading the model weights. For more details, check out their technical report here: https://lnkd.in/djMUhED8 The Mixtral8x7B LLM is remarkably powerful, and this tool enhances its accessibility, particularly in scenarios where cloud-based models are impractical due to the need to handle sensitive information. You can check out the code here: https://lnkd.in/dnSF_qzv

Glad to see these hardware enhancements are now a set of Vulkan GLSL extensions. They save both power and time in these common image processing requirements. https://lnkd.in/eDmqFt7W

#Day57 of the 100 RTL days Challenge : Cracking the Code of a 4-to-1 Mux! 💡 Today's challenge involved studying simulation waveforms to decode the functionality of a 4-to-1 multiplexer. Understanding how the circuit navigates and selects inputs sheds light on its purpose. Now, equipped with this insight, it's time to implement the magic of the mux in the digital realm. #SystemVerilog #DigitalDesign #Verification #XilinxVivado  #100rtldayschallenge #ieeecasskerala #ieeecasssahrdaya

I'm happy to share this article we published at the end of last year (2023) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI). This article presents an AV1 intra-prediction decoder called AVID, which is a dedicated high-throughput hardware design for the AV1 decoder intra-prediction supporting the AV1 68 prediction modes and 19 block sizes. This paper reports the main results reached by Jones Goebel in his master's course at Video Technology Research Group (ViTech). The proposed architecture can decode UHD 4K videos at 120 frames/s. This was the first article detailing the hardware design of a complete decoder for intra-prediction targeting the AV1 codec. The other authors are: myself, Bruno Zatt, and Marcelo Porto. The paper is available at:

#NDF researchers register a new patent. #NDF researchers Bernardo Lemos, Professor Julio Romano Meneghini, Rodrigo de Lima Amaral and Vítor Augusto Andreghetto Bortolin developed a support that allows the combined use of up to four cameras, which are cheaper and more accessible, to monitor patterns, processes and equipment using time-resolved image analysis. The images captured by the combined low-frequency cameras are in color and have a high spatial resolution, which differentiates them from traditional high temporal resolution systems, which are more expensive and monochrome. In addition, the technology is suitable for monitoring/inspecting industrial, commercial and residential environments, as it is compact. Check it out: https://bit.ly/3xKdEB1 Learn more about us at https://bitly.ws/3fxC5 #NDF #USP

We've got a new version of #HIP #Raytracing available on GPUOpen! h Featuring: Batch BVH construction Dynamic traversal stack assignment Transformation query functions .. and more. Great job Daniel Meister and Paritosh Kulkarni, and Takahiro Harada

[NEW REPORT] Who are the leaders at the forefront of Versatile Video Coding (VVC) innovation? Find out in our brand new report: “Who is Leading the VVC Patent Race?”. We are excited to provide a comprehensive view of leading regions, market opportunities, SEP implications, and key considerations for the future for this technology area that is evolving at lightning speed. Download the report here: https://hubs.ly/Q02Dn5vc0 #PatentAnalytics #SEP #VVCPatents #VVCTechnology