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TrendForce forecasts that the AI server liquid cooling market will experience rapid growth, driven by the launch of NVIDIA's Blackwell platform and ASIC upgrades, with penetration rate projected to reach 20-30% by 2025. Blackwell's high performance and power consumption will accelerate the adoption of liquid cooling solutions, prompting ODMs, power supply, and cooling solution providers to actively expand into the liquid cooling market. Additionally, the rising global awareness of ESG and CSPs' investments in AI servers will further promote liquid cooling technology. Due to trade conflicts, cooling suppliers are accelerating expansion in Southeast Asia to seize growth opportunities in the AI accelerator and liquid cooling markets.
(a) incentives for chip makers to adopt FOPLP solution: AI GPU makers pursuing chip packaging size expansion could adopt chip-last solution, while power IC and RF IC makers pursuing packaging cost reduction could adopt chip-first solution. The segmented market could accommodate different types of suppliers.
(b) development of FOPLP solution by foundry: expanding chip packaging size of 2.5D packaging for AI GPU from wafer level to panel level.
(c) development of FOPLP solution by OSATs: migrating from power IC and RF IC to CPU and GPU, enabling multi-chip packaging.
(d) development of FOPLP solution by panel makers: entry into chip packaging business, supported by licencers.
1. An Overview of the Semiconductor Market
2. Demand & Capacity Utilization
3. Supply & Geopolitical Impact
4. The Semiconductor Market in the Age of AI
5. TRI’s View
1. New Era for Japanese Semiconductor Industry: Innovations and Development Trends under Governmental Interventions
2. TRI's View
As indicated by the survey of global market intelligence firm TrendForce, chip suppliers such as AMD have been actively involved in negotiations with TSMC and OSAT throughout 2Q24 on chip packaging using the FOPLP technology, with major partnership models and items shown below:
Model 1: OSATs transitioning from traditional packaging method to FOPLP when packaging consumer ICs: AMD is currently negotiating with PTI and ASE on PC CPUs, whereas Qualcomm is talking it over with ASE on PMIC. Prior to this wave of demand, MediaTek had been worked with PTI on PMIC, while Qualcomm was already a partner of ASE pertaining to PMIC.
Model 2: foundries and OSATs transitioning from 2.5D wafer level to panel level when packaging AI GPUs: AMD and NVIDIA are currently negotiating with TSMC and SPIL on packaging AI GPUs by switching from the existing 2.5D wafer level to panel level, followed by an expansion in chip packaging sizes.
Model 3: panel providers packaging consumer ICs: NXP and STMicroelectronics are negotiating with Innolux on PMIC products.
Optical module is an indispensable component for achieving optical communication. However, corresponding issues are becoming increasingly apparent alongside the continuously climbing usage and growing transmission performance. This report, aside from probing into the development bottlenecks of existing optical module solutions, also focuses on the dynamics of three major solutions - LPO, OBO, and CPO - and their supply chains.
Under the influence of growing AI-related demand and the slowing pace of node migration under Moore’s Law, achieving lower power consumption and higher transistor counts on a single chip has become a major challenge. To address this, 3D stacking architecture has emerged as a key technology. TSMC anticipates that within the next several years, a single chip could contain as many as 200 billion transistors. Furthermore, TSMC aims to reach a milestone of over 1 trillion transistors through 3D packaging.
As the AI chip architectures for the integration of memory and logic ICs advance from 2.5D to 3D, breakthroughs in the development of hybrid bonding will be critical. This report examines the implications of these technological advancements, focusing on the growth in the demand for hybrid bonding and related processes as well as how this trend affects equipment providers.
TSMC president C.C. Wei was questioned by analysts about the potential introduction of High-NA EUV during TSMC’s 4Q23 earnings call. He responded, “Because of technology itself is no value. Only when that can serve your customer. So we always work with our customers to give them the best transistor technology and the best power-efficient technology and at a reasonable cost, okay? And more importantly, the technology maturity that—in the high-volume production, that's all important. Everything. Everything counted together. So we—every time we know that there are some new structure, new tools such a high-NA EUV, we look at it carefully, look at the maturity of the tools, look at the cost of the tools and look at the schedule of that—how to achieve it. We always make the right decision at the right moment to serve our customers.”
1. Status-quo of the Cloud AI Chip Market
2. Developments of Cloud AI Chipmakers Worldwide
3. Developments of CSPs’ Self-designed AI Chips
4. TRI’s View
FPGAs have diverse functions and are widely used in various fields, and is increasing in importance with the continuous advancement of electronic devices. This report mainly analyzes the product characteristics of FPGAs, explores their long-term development trends, and also focuses on the development dynamics of the global FPGA market and key suppliers.